Multi-Rank Memory Built-In Self-Test Status via DMI Bits
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Solution Overview
Problem
Memory devices with multiple ranks face inefficiencies in performing built-in self-tests (MBIST) due to the need for separate testing of each rank, which can prolong test times and disrupt standard operations, and existing solutions may require additional pins or reconfiguration, violating industry standards.
Innovation Solution
Utilizing multiple DMI bits to indicate the status of MBIST for each rank independently, allowing simultaneous testing of multiple ranks without requiring additional pins, thus optimizing performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate testing is performed for each rank, then testing completeness is ensured, but test time increases
Solution Approach 1:
The patent combines multiple rank testing operations into a single simultaneous MBIST execution. Multiple DMI bits are used to independently indicate MBIST status for each rank, enabling the memory device to perform built-in self-test on multiple ranks concurrently rather than sequentially, thus reducing total test time while maintaining comprehensive testing coverage.
Solution Approach 2:
The patent segments the MBIST status indication into multiple independent DMI bits, with each bit corresponding to a specific rank. This segmentation allows independent monitoring and control of test status for each rank, enabling simultaneous testing operations without interfering with each other.
2Loss of information
If additional pins are added for status indication, then MBIST status can be indicated for each rank, but device complexity increases and industry standard compliance is violated
Solution Approach 1:
The patent makes the existing DMI pins multi-functional by enabling them to serve both their original data mask inversion function and the additional function of indicating MBIST status for respective ranks. This eliminates the need for separate dedicated pins for status indication, maintaining compliance with industry standards while achieving comprehensive status monitoring.
Solution Approach 2:
The patent dynamically reconfigures the function of DMI pins based on operational context. The same physical pin can serve different purposes (data mask inversion during normal operation, MBIST status indication during testing), allowing flexible functionality without additional hardware.
Data Source
AI summary
Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.