Multi-Rank Memory Power Control for High-Speed Access
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Solution Overview
Problem
Existing memory systems with multiple ranks face challenges in balancing power consumption and high-speed operation performance due to inefficiencies in rank interleaving and idle power states, leading to increased current consumption and operational delays.
Innovation Solution
A memory controller is employed to manage power states by causing memory ranks to enter idle power down (IPD) or active power down (APD) states based on data toggle times and page access patterns, utilizing a power-down control circuit to optimize power usage and reduce delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory ranks are kept in idle non-power down or active non-power down state to maintain high-speed operation readiness, then operation speed is improved, but power consumption increases due to continuous current draw (IDD2N or IDD3N)
Solution Approach 1:
The patent implements dynamic power state management by transitioning memory ranks between idle non-power down, idle power down, and active power down states based on access patterns. The controller dynamically determines when to enter or exit power down states, optimizing the balance between speed readiness and power consumption rather than maintaining a static state.
Solution Approach 2:
The patent changes the power state parameter of memory ranks based on timing conditions. By monitoring whether the current access bank will be accessed again within a threshold time period, the system adjusts the power state (between IPD and APD) to achieve optimal power consumption while maintaining operational requirements.
2Productivity
If frequent rank interleaving operations are performed to maintain memory access efficiency, then productivity is improved, but power consumption increases and operational delays occur due to switching between ranks
Solution Approach 1:
The patent performs preliminary assessment of future access patterns before executing rank switching operations. By determining whether the current access bank will be accessed again within a threshold time, the system proactively decides to maintain or transition power states, avoiding unnecessary rank interleaving operations and their associated power consumption and delays.
3Use of energy by moving object
If memory ranks enter idle power down or active power down state to reduce current consumption, then power consumption is reduced, but operational delays increase due to wake-up time requirements
Solution Approach 1:
The patent implements feedback control by continuously monitoring access patterns and timing information. The controller determines whether to enter or exit power down states based on whether the current access bank will be accessed again within a threshold time period, creating a closed-loop system that adapts to actual usage patterns and minimizes both power consumption and operational delays.
Data Source
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AI summary
Provided are electronic devices and methods for power reduction in systems with multiple memory ranks. The electronic device includes a memory system including first and second memory ranks and a memory controller connected to the memory system and configured to control power of the memory system. The memory controller being configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank.