Multi-Rank Memory Scheduling for Lower Access Latency
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Solution Overview
Problem
The performance improvement of multi-core processor systems is limited due to increased main memory access latency as the number of processor cores increases, necessitating a method to enhance memory access performance.
Innovation Solution
A memory system with multiple memory ranks and a memory controller that performs counting operations, rank transition, and scheduling to optimize memory access by selecting a target memory rank based on request readiness states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of processor cores is increased to improve computing power, then computing power is improved, but main memory access latency increases
Solution Approach 1:
The memory system is segmented into multiple independent memory ranks (first memory rank, second memory rank, etc.), each capable of independent operation. The memory controller divides memory access requests and distributes them to different memory ranks, allowing parallel processing of memory operations. This segmentation enables the system to maintain low access latency even with increased processor cores by providing multiple concurrent access paths to memory.
2Productivity
If multiple memory ranks are introduced to improve memory access performance, then memory access performance is improved, but device complexity increases
Solution Approach 1:
The memory controller is designed with multi-functional capabilities to manage multiple memory ranks. It incorporates a counting circuit that can simultaneously count requests for different memory ranks, a comparing circuit that can compare counting values across ranks, and a rank transition circuit that can switch between ranks. This universal design allows the controller to handle diverse memory access patterns and manage multiple ranks without proportionally increasing complexity, as the same structural elements serve multiple functions.
3Productivity
If a counting operation is performed on available requests for each memory rank to select a target memory rank, then memory access performance is improved, but operation complexity increases
Solution Approach 1:
The counting circuit performs preliminary counting of available requests for each memory rank before the actual memory access operation. By pre-counting requests and maintaining these counts in ready state, the system prepares scheduling information in advance. This preliminary action allows the comparing circuit to quickly determine which memory rank has the most requests without performing complex real-time analysis during the access operation, thereby simplifying the scheduling process while improving performance.
Data Source
AI summary
A memory system includes a plurality of memory ranks, and a memory controller configured to control the plurality of memory ranks. The memory controller performs scheduling such that a request to be processed first is selected based on a counting value obtained by counting requests with the plurality of memory ranks as target memory ranks.