Multi-rank Receiver Digital Transistor Control
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Solution Overview
Problem
Conventional multi-rank circuit systems face challenges with circuit area consumption and complexity due to the need for multiple reference voltage generators and control signals, which complicates layout and routing, and limits fast rank switching due to the analog nature of reference voltages.
Innovation Solution
A global reference voltage generator provides a range of voltages to local reference voltage generators, reducing the number of control signals and allowing digital control of transistor strength in receivers for fine-tuning, enabling faster rank switching and reduced circuit area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple per-pin reference voltage generators are used for each rank, then each receiver can be adjusted with an optimum VREF to account for process variations, but the circuit area consumption increases substantially
Solution Approach 1:
The patent merges multiple per-pin reference voltage generators into a single shared reference voltage generator that serves all receivers. This consolidation reduces circuit area while maintaining the ability to provide optimized reference voltages through digital control of transistor strength in each receiver, resolving the contradiction between precision adjustment and area consumption.
Solution Approach 2:
The patent changes the control mechanism from analog reference voltage adjustment to digital control of transistor strength. By using digital control signals to adjust the effective transistor strength in parallel branches, the system achieves fine-tuning capability without requiring multiple analog reference voltage generators, thus reducing area while maintaining measurement precision.
2Adaptability or versatility
If multiple per-pin reference voltage generators are used for each rank, then each receiver can operate with its own VREF, but the circuit layout and routing complexity increases
Solution Approach 1:
The patent combines multiple independent reference voltage generators into a single shared generator, significantly simplifying layout and routing. Receivers maintain their independence through digital control of transistor strength rather than through separate analog reference voltage sources, reducing layout complexity while preserving receiver adaptability.
Solution Approach 2:
The patent replaces the analog reference voltage adjustment mechanism with a digital control system that adjusts transistor strength. This substitution eliminates the need for complex analog routing and reduces layout complexity, as digital control signals can be distributed more easily than analog reference voltages.
3Adaptability or versatility
If multiple per-pin reference voltage generators are used for each rank, then each receiver has its own VREF, but the number of control signals increases significantly
Solution Approach 1:
The patent merges the control functions of multiple reference voltage generators into a single control system. Instead of requiring separate control signals for each per-pin generator, the system uses a shared generator with digital control signals that adjust transistor strength in each receiver, dramatically reducing the total number of control signals while maintaining receiver configurability.
Solution Approach 2:
The patent changes from controlling multiple analog reference voltage generators to digitally controlling transistor strength parameters in receivers. This parameter change allows for more efficient control signal usage, where digital codes can selectively activate or adjust the strength of specific transistor branches to achieve the desired receiver configuration.
4Measurement precision
If the reference voltage is changed when switching ranks, then the reference voltage can be optimized for each rank, but the analog reference voltage may not settle fast enough to enable fast rank switching
Solution Approach 1:
The patent replaces the analog reference voltage switching mechanism with a digital control system that adjusts transistor strength. This substitution eliminates the settling time issue inherent in analog reference voltage changes, as digital control signals can be switched instantaneously while maintaining optimized reference voltages through controlled transistor activation.
Solution Approach 2:
The patent introduces dynamic control of transistor strength through digital signals, allowing the system to rapidly switch between rank configurations. By controlling the effective strength of transistors in parallel branches rather than switching analog reference voltages, the system achieves fast rank switching while maintaining optimized voltage levels for each rank.
5Speed
If multiple receivers are provided for each rank with preconfigured VREF values, then fast rank switching can be achieved, but the area and power costs become prohibitive
Solution Approach 1:
The patent merges multiple rank-specific receivers into a single shared receiver structure with digitally controlled transistor branches. Instead of providing separate preconfigured receivers for each rank, the system uses a single receiver that can be dynamically configured through digital control of transistor strength, achieving fast rank switching without the area and power costs of multiple receivers.
Solution Approach 2:
The patent creates a universal receiver structure that can serve multiple ranks through digital control of transistor strength. The single receiver with parallel transistor branches can be dynamically configured to handle different rank requirements, providing multi-functionality that eliminates the need for separate dedicated receivers for each rank, thus reducing area and power consumption.
Data Source
AI summary
A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.