Multi-rate Parallel Circuit Simulation for Nanometer Design
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Solution Overview
Problem
Conventional circuit simulation methods, such as SPICE, face challenges in efficiently simulating large-scale integrated circuits due to increased matrix complexity and computational costs, limiting their practicality for full chip design and nanometer-scale device geometries.
Innovation Solution
The implementation of multi-rate parallel circuit simulation, which partitions the circuit into groups with distinct simulation time steps, allowing for parallel processing and dynamic load balancing to optimize computational efficiency and reduce simulation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SPICE circuit simulation is used to simulate whole systems, then simulation accuracy is maintained, but simulation time becomes excessively long and computational complexity increases
Solution Approach 1:
The circuit is divided into multiple partitions, each with its own simulation time step. This segmentation allows different parts of the circuit to be simulated at different rates, reducing the overall simulation time while maintaining accuracy where needed. The circuit partitioning creates independent simulation domains that can be processed in parallel.
Solution Approach 2:
The simulation uses dynamic time step adjustment where each partition can have its own time step size. Fast-changing regions use smaller time steps for accuracy, while slow-changing regions use larger time steps to reduce computation time. This dynamic approach optimizes the trade-off between accuracy and speed.
2Productivity
If circuit size increases with nanometer device geometries, then design capability is improved, but matrix complexity and computational burden increase
Solution Approach 1:
The large circuit matrix is segmented into multiple smaller partition matrices. Each partition is solved independently with its own time step, reducing the complexity of individual matrix operations. The partitions are then combined to form the complete circuit solution, enabling handling of large-scale nanometer designs.
Solution Approach 2:
The simulation adds a temporal dimension by using multi-rate time steps. Instead of solving one large matrix at a single time step, the system solves multiple smaller matrices at different time steps, effectively transforming the computational problem into a multi-dimensional space that is more manageable.
3Ease of operation
If uniform time step is used for entire circuit simulation, then implementation simplicity is maintained, but computational efficiency decreases
Solution Approach 1:
Different time steps are assigned to different circuit partitions based on their local characteristics. Regions with fast transient behavior use smaller time steps, while regions with slow behavior use larger time steps. This local optimization improves computational efficiency without sacrificing accuracy in critical regions.
Data Source
AI summary
Methods and systems are disclosed related to multi-rate parallel circuit simulation. In one embodiment, a computer implemented method of partitioning the circuit into a plurality of partitions, wherein each partition is represented by a set of linear differential equations, determining a simulation time step for each partition of the plurality of partitions, grouping the plurality of partitions into multiple groups, wherein each group includes one or more partitions having simulation time steps within a predefined range of each other, and solving the multiple groups with their corresponding simulation time steps in parallel.