Multi-Rate Clock Buffer Using Selective Tuned Circuits

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Solution Overview

Problem

Clock buffers tuned for specific frequencies exhibit reduced performance when encountering clock signals at different frequencies, leading to increased power consumption and reduced efficiency when handling multiple frequency inputs.

Innovation Solution

A multi-rate clock buffer circuit is designed with a driver circuit and two tuned circuits, each configured for different frequency ranges, allowing the circuit to be active within specific frequency ranges and inactive outside them, enabling support for multiple clock signal frequencies without interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the clock buffer is tuned to a specific clock signal frequency, then power consumption is reduced, but performance deteriorates when the clock signal frequency varies

Engineering Contradiction:

Improvepower consumptionVSAvoidperformance across frequency ranges

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The clock buffer is divided into multiple tuned circuits, each optimized for a specific frequency range. Instead of using a single tuned circuit that can only operate efficiently at one frequency, the system segments the buffering function across multiple frequency-specific circuits (e.g., first tuned circuit for first frequency range, second tuned circuit for second frequency range), allowing the buffer to maintain optimal performance across varying frequencies.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The clock buffer system is designed to perform multiple functions by incorporating tuned circuits that can handle different frequency ranges. The system universally processes clock signals regardless of their specific frequency by routing them to the appropriate tuned circuit based on frequency matching, making the buffer adaptable to various operating conditions while maintaining efficiency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple tuned circuits are used to support different frequency ranges, then adaptability improves, but device complexity increases

Engineering Contradiction:

Improvesupport for multiple frequency rangesVSAvoidcircuit structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system dynamically selects which tuned circuit to activate based on the input clock signal's frequency. Control logic monitors the incoming clock signal and enables only the tuned circuit whose frequency range matches the input signal, dynamically adjusting the active circuit configuration. This dynamic operation allows multiple tuned circuits to coexist without simultaneously processing signals, thereby managing complexity through selective activation rather than requiring all circuits to be permanently engaged.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10361687B2Multi-rate clock buffer

Publication Date: 2019.07.23 II VI DELAWARE INC

AI summary

A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.