Multi-Rate Data Converter Clocking for Precise Channel Alignment
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Solution Overview
Problem
Conventional test and measurement instruments face challenges in achieving high sample rates without increasing cost, complexity, power consumption, and size, particularly when multiple digitizers are required, and maintaining precise alignment of different sample rate clocks is difficult.
Innovation Solution
A system with a universal timing control that generates synchronized fast and slow clocks from a common intermediate frequency clock, using Phase-Locked Loops or frequency multipliers to minimize jitter, and a universal trigger control for coordinating triggers across channels with different sample rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple digitizers are multiplexed to achieve higher sample rates, then the sample rate capability is improved, but the cost and complexity of each channel increases
Solution Approach 1:
The system divides channels into two segments: high-speed channels that sample at the higher rate and low-speed channels that sample at the lower rate. This segmentation allows the instrument to achieve high sample rate capability without requiring all channels to use multiple multiplexed digitizers, thereby reducing per-channel complexity while maintaining overall high-speed capability.
Solution Approach 2:
Different channels are assigned different sampling rates based on their specific requirements. High-speed channels receive the higher sampling rate from the fast clock, while low-speed channels receive the lower sampling rate from the slow clock. This local differentiation optimizes resource allocation and reduces unnecessary complexity in channels that do not require high-speed sampling.
2Speed
If multiple digitizers are multiplexed to achieve higher sample rates, then the sample rate capability is improved, but the power consumption and heat generation increase
Solution Approach 1:
The system segments the operation into high-speed and low-speed modes, activating only the necessary digitizers and clock circuits for each mode. When high sample rate is required, only the fast clock and relevant high-speed channels are activated, while low-speed channels remain inactive or operate at lower power, thereby reducing overall power consumption compared to keeping all digitizers running at high speed.
Solution Approach 2:
The system dynamically switches between using the slow clock and fast clock based on the sampling rate requirements of active channels. This dynamic operation allows the instrument to consume less power when high-speed sampling is not needed, while still providing the capability to achieve high sample rates when required by activating the fast clock and associated high-speed channels.
3Speed
If multiple digitizers are multiplexed to achieve higher sample rates, then the sample rate capability is improved, but the device size increases
Solution Approach 1:
The system segments the digitizer resources into high-speed and low-speed groups, allowing a single instrument to serve multiple market segments. By sharing the same physical hardware resources between high-speed and low-speed channels, the system achieves high sample rate capability without proportionally increasing device size, as the same digitizers are time-multiplexed between different operating modes.
Solution Approach 2:
The instrument is designed with universal hardware resources that can operate in multiple modes. The same digitizers and processing circuits can function in both high-speed and low-speed configurations, allowing the device to provide high sample rate capability when needed while maintaining a compact form factor suitable for midrange applications, rather than requiring separate dedicated high-speed and low-speed instruments.
4Adaptability or versatility
If independent clocks are used for high and low sample rate channels, then each channel can operate at its required rate, but keeping the clocks aligned with precision is difficult
Solution Approach 1:
The system introduces a common base oscillator as an intermediary reference for both the slow clock and fast clock. The slow clock is derived directly from the base oscillator, while the fast clock is generated by multiplying the base oscillator frequency. This intermediary reference ensures that both clocks maintain a precise mathematical relationship and remain aligned, solving the synchronization problem that would exist with completely independent clock sources.
Solution Approach 2:
The system changes the frequency parameter of the base oscillator to generate different clock rates. By using a base oscillator at a specific frequency and multiplying it by different factors, the system generates both the slow clock and fast clock from the same reference, ensuring their frequencies are precisely related. This parameter-based approach maintains clock alignment while providing the flexibility to operate at different sample rates.
5Stability of the object's composition
If the slow clock is multiplied to produce the fast clock, then the fast clock can be generated from the same base oscillator, but the jitter is significantly magnified
Solution Approach 1:
The system uses the base oscillator as an intermediary to generate both clocks independently rather than multiplying the slow clock. The fast clock is generated by multiplying the base oscillator frequency, not the slow clock frequency. This intermediary approach breaks the jitter multiplication chain, as the multiplication is performed on the cleaner base oscillator signal rather than on the already-noisy slow clock signal, thereby reducing the overall jitter in the fast clock.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient, synchronized sampling and triggering of signals with varying sample rates, reducing costs and complexity while maintaining precise alignment, thus enhancing the performance of high-channel count test and measurement instruments.
Implementation Method 1
generating a fast clock from the intermediate frequency clock with minimal jitter, and generating a slow clock from the intermediate frequency clock with minimal jitter
Data Source
AI summary
A test and measurement instrument includes a first data channel including a first data converter operating at a first rate, and a second data channel including a second data converter operating at a second rate that is different than the first rate. Rate controls may include a clock generation circuit. The clock generation circuit includes an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, and a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock. The first frequency clock may be used to control the rate of the first data channel, and the second frequency clock may be used to control the rate of the second data channel. Methods are also described.