Multi-Rate Receiver Equalizer With Clock Gating for Lower Power
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Solution Overview
Problem
Current multi-rate receivers face increased circuit complexity and power consumption due to the need to support various sampling rates and transmission speeds, particularly in interface technologies like PCIe, where clock generating circuits and equalizers become more complex and power-intensive.
Innovation Solution
A receiver design that includes an equalization circuit for outputting data and edge sample signals using a multi-phase clock signal and a clock gate circuit to select the appropriate multi-phase clock signals based on a selection signal, reducing circuit complexity and power consumption by optimizing clock signal usage across different generations of interface standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock generating circuit that generates a wide range of frequencies is used to support various sampling rates, then the receiver can support multiple transmission speeds, but the area of the clock generating circuit increases because additional circuits are used
Solution Approach 1:
The patent implements a universal clock generating circuit that can operate across multiple frequency ranges (e.g., 2.5GHz, 5GHz, 8GHz, 16GHz, 32GHz) using the same hardware infrastructure. The circuit uses a single Phase Locked Loop (PLL) and Delay Locked Loop (DLL) that can be dynamically configured to generate different clock frequencies, eliminating the need for separate dedicated circuits for each sampling rate and thereby reducing overall circuit area.
Solution Approach 2:
The patent employs dynamic frequency selection mechanisms where the clock generating circuit can adaptively switch between different operating frequencies based on the required sampling rate. This is achieved through dynamic control of the PLL and DLL circuits, allowing the same hardware to be reconfigured in real-time to support different transmission speeds without requiring additional static circuitry for each frequency.
2Adaptability or versatility
If additional circuits are added to support various sampling rates, then the receiver can handle multiple transmission speeds, but the structure of the equalizer becomes complicated and power consumption increases
Solution Approach 1:
The equalizer is designed as a universal structure that can operate effectively across multiple sampling rates using the same hardware components. The equalizer circuits are configured to work with clock signals of varying frequencies generated by the multi-rate PLL and DLL, allowing a single equalizer design to serve multiple transmission speeds without requiring separate dedicated equalizer circuits for each rate, thereby simplifying the overall structure.
Solution Approach 2:
The patent utilizes parameter changes in the equalizer configuration to adapt to different sampling rates. By dynamically adjusting equalizer parameters such as tap weights, filter coefficients, and clock phase offsets based on the operating frequency, the same equalizer hardware can optimally perform across various transmission speeds without structural modification, reducing complexity while maintaining adaptability.
3Adaptability or versatility
If additional circuits are added to support various sampling rates, then the receiver can handle multiple transmission speeds, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management in the clock generating circuit and equalizer where components are activated or deactivated based on the required operating frequency. The PLL and DLL circuits can dynamically adjust their operation modes, and the equalizer can switch between different configuration states, allowing the receiver to consume only the necessary power for the current transmission speed rather than continuously powering all possible frequency-generating circuits, thereby reducing overall power consumption while maintaining multi-rate support.
Data Source
AI summary
A receiver includes an equalization circuit configured to output a data sample signal and an edge sample signal by sampling a data input signal according to clock signal, and to perform an equalization operation according to the data sample signal and the edge sample signal; and a clock gate circuit configured to select the clock signals from among a plurality of multi-phase clock signals according to a selection signal.