Multi-Rate Synchronization Clock Circuit for Aligned Frame Starts
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Solution Overview
Problem
Conventional augmented reality display systems face challenges in synchronizing operations among devices with different frame rates, particularly between displays and sensing devices.
Innovation Solution
A synchronization signal generation circuit and method that utilizes a clock signal generator and a first controller to generate candidate clock signals aligned with a reference clock signal, selectively transmitting these signals to peripheral devices based on their frame rate requirements, ensuring aligned start time points within each frame period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If devices operate at different frame rates independently, then each device can optimize its performance, but synchronization between devices deteriorates
Solution Approach 1:
The patent segments the clock signal generation by creating multiple independent counter units (first counter, second counter, third counter) that can operate at different frame rates simultaneously. Each counter generates clock signals for specific devices, allowing independent optimization while maintaining system-wide synchronization through a unified reference clock signal.
Solution Approach 2:
The patent changes the frame rate parameter dynamically by selecting different counter units based on device requirements. The controller can switch between 60Hz, 30Hz, and other frame rates for different devices by activating appropriate counters, enabling each device to operate at its optimal frame rate while maintaining synchronization.
2Reliability
If a unified clock signal is used for all devices, then synchronization is improved, but adaptability to different frame rate requirements deteriorates
Solution Approach 1:
The patent divides the single clock signal distribution into multiple segmented paths, each with its own counter unit configured for specific frame rates. This segmentation allows the system to provide synchronized clock signals tailored to each device's frame rate requirements, combining both synchronization and adaptability.
Solution Approach 2:
The patent creates a multi-functional clock signal generation system where a single reference clock signal serves multiple purposes through different counter units. The same reference clock is used to generate 60Hz, 30Hz, and other frame rate signals, making the system universally compatible with various device requirements while maintaining synchronization.
3Adaptability or versatility
If multiple clock signals are generated for different frame rates, then adaptability improves, but system complexity increases
Solution Approach 1:
The patent segments the clock generation function into modular counter units, where each counter is a simple, standardized component. This segmentation reduces overall complexity by using repetitive, simple building blocks rather than complex custom circuits for each frame rate.
Solution Approach 2:
The counter units are designed to automatically generate the appropriate clock signals based on their inherent counting logic. Each counter self-generates its specific frame rate signal from the reference clock without requiring complex external control logic, reducing system complexity while maintaining adaptability.
Data Source
AI summary
A synchronization signal generation circuit and a synchronization method among a plurality of devices are proposed. The synchronization signal generation circuit includes a clock signal generator and a controller. The clock signal generator generates a reference clock signal. The controller receives an input clock signal from a host end device and generates a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal. The controller selectively transmits one of the candidate clock signals to each peripheral device according to request information corresponding to each peripheral device. The candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.