Multi-RDL Semiconductor Package for Compact Thermal Performance

The patent transitions from a single-layer monolithic QFN package to a multi-layer stacked package architecture with multiple chips arranged vertically. This dimensional change allows heat dissipation surfaces to be distributed across multiple layers, effectively increasing the total heat dissipation area without increasing the package footprint, thus resolving the contradiction between reduced package size and maintained heat dissipation capability.

The patent divides a single large chip into multiple smaller chips arranged in a stacked configuration. Each chip can be independently optimized for thermal performance, and the segmented arrangement creates multiple heat dissipation pathways. This segmentation allows the package to maintain effective heat dissipation across a reduced overall size by distributing thermal loads across multiple discrete components.

The patent employs a nested layering structure where multiple chips are stacked vertically with molding layers embedded between them. Each chip-molding layer combination is nested within the overall package structure, creating a compact hierarchical arrangement. This nesting approach maximizes the chip-surface to package-surface ratio while maintaining a relatively streamlined external form factor, balancing thermal performance improvement with structural complexity management.

By transitioning to a three-dimensional stacked architecture with multiple layers, the patent increases the effective chip surface area within a compact footprint. The vertical stacking in the Z-dimension allows multiple chips to be integrated without proportionally increasing the X-Y plane footprint, thereby improving thermal performance while controlling the overall package volume and structural complexity.