Multi-Recessed Shallow Trench Isolation for IC Junction Optimization
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Solution Overview
Problem
The existing shallow trench isolation (STI) techniques in integrated circuits face challenges in optimizing junction isolation and process windows due to the use of a single trench depth for various semiconductor devices, which can lead to reduced performance and increased complexity in design and fabrication.
Innovation Solution
The method involves forming shallow trench isolation structures of different depths based on the characteristics of semiconductor devices, allowing for optimized junction isolation and relaxation of STI stress, and narrowing the gap fill and CMP process windows by using multiple depths for STI structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single trench depth is used for all STI structures, then the fabrication process is simpler, but the junction isolation optimization for different semiconductor devices is compromised
Solution Approach 1:
The patent applies local quality by creating STI structures with different trench depths tailored to specific device requirements. First trenches are formed to a first depth for first semiconductor devices, while second trenches are formed to a second depth for second semiconductor devices. This allows each device type to have optimized isolation depth, improving junction isolation while maintaining a relatively simple single-step fabrication process using selective masking techniques
2Reliability
If multiple trench depths are used for different semiconductor devices, then junction isolation optimization is improved, but the fabrication process complexity increases
Solution Approach 1:
The patent merges multiple STI formation operations into a single integrated process. Instead of performing separate trench formation steps for different depths, the invention combines first trench formation and second trench formation into one fabrication sequence using selective masking and etching techniques. This reduces the number of discrete process steps while achieving multi-depth isolation structures, thereby improving junction isolation without proportionally increasing fabrication complexity
3Manufacturing precision
If a uniform STI depth is used, then the process window is larger, but the STI stress relaxation is insufficient
Solution Approach 1:
The patent applies parameter changes by varying the trench depth parameter across different STI structures. First trenches have a first depth while second trenches have a second depth, allowing stress relaxation optimization for different device regions. This parameter variation enables better stress management while maintaining a robust fabrication process window through controlled single-step formation
Data Source
AI summary
A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.