Multi-Reference Comparator for Low-Voltage DRAM Equalization
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Solution Overview
Problem
Existing comparators in mobile devices fail to meet the requirements for lower operating voltage and energy consumption, which is essential for dynamic random access memory (DRAM) data reading and writing.
Innovation Solution
A comparator design comprising multiple sampling and output circuits controlled by control signals and clock signals, generating differential signals using reference signals of varying voltages to ensure consistent polarity and accurate comparison results, thereby reducing intersymbol interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing comparator designs are used, then device complexity is reduced, but power consumption is too high and operating voltage cannot be lowered
Solution Approach 1:
The comparator is divided into multiple independent sampling circuits (first sampling circuit, second sampling circuit, third sampling circuit, fourth sampling circuit), each handling different reference signal levels. This segmentation allows each circuit to operate independently at optimized voltage levels, reducing overall power consumption while maintaining comparison accuracy through coordinated operation of all segments.
Solution Approach 2:
The invention dynamically changes the reference signal parameters by selecting different reference signals (first reference signal, second reference signal, third reference signal, fourth reference signal) with different voltage levels based on the input signal characteristics. This parameter adaptation enables the comparator to operate at lower voltages for small signals while maintaining accuracy for large signals, directly addressing the power consumption vs. accuracy trade-off.
2Object-affected harmful factors
If single reference signal comparison is used, then device complexity is low, but intersymbol interference cannot be effectively reduced
Solution Approach 1:
The comparison process is segmented into multiple parallel paths, each comparing the input signal against a different reference signal level. The first sampling circuit compares against the first reference signal, the second against the second reference signal, and so on. This segmented multi-level comparison effectively captures signal characteristics across different amplitude ranges, reducing intersymbol interference by providing comprehensive signal characterization.
Solution Approach 2:
The invention implements feedback mechanisms where the output of each sampling circuit influences the operation of subsequent circuits. The control signals generated from previous comparison stages feed back to adjust the operation of later stages, enabling adaptive cancellation of intersymbol interference through iterative refinement of the comparison results.
3Measurement precision
If higher operating voltage is used, then comparison accuracy is improved, but energy consumption increases
Solution Approach 1:
Different parts of the comparator (different sampling circuits) are assigned different quality characteristics and voltage levels according to their specific functions. The first sampling circuit operates at one voltage level for its specific comparison task, while the second sampling circuit operates at a different voltage level suited to its function. This local optimization allows each circuit to achieve sufficient accuracy at the minimum necessary voltage, reducing total energy consumption while maintaining overall comparison precision.
Data Source
AI summary
The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit provided with an output terminal, and configured to generate, under the control of a first control signal and a clock signal, a first differential signal according to a signal to be compared and a first reference signal; a second sampling circuit provided with an output terminal connected to the output terminal of the first sampling circuit, and configured to generate, under the control of a second control signal and the clock signal, a second differential signal according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal.