Multi-Reference Layer MRAM Cell for High-Speed Read
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Solution Overview
Problem
Magnetic domain wall motion type MRAMs face challenges in achieving high-speed read operations while maintaining a reduced memory cell size, as existing structures that reduce interconnection capacitance for high-speed read operations tend to increase the memory cell area.
Innovation Solution
The implementation of a magnetic random access memory (MRAM) cell structure with multiple reference layers and tunnel barrier films, where each memory cell includes a magnetic recording layer and multiple reference layers with fixed magnetizations, connected to read bitlines, allowing for high-speed read operations while minimizing the memory cell area by storing two-bit data in a single cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory cell structure uses multiple reference layers and tunnel barrier films to reduce interconnection capacitance for high-speed read operations, then the read speed is improved, but the memory cell area increases
Solution Approach 1:
The patent transitions from a single reference layer structure to a multi-layer reference layer structure, adding the dimension of vertical stacking. Multiple reference layers (first reference layer, second reference layer, third reference layer) are positioned at different heights relative to the magnetic recording layer, with tunnel barrier films separating them. This vertical arrangement allows multiple MTJs to share read bitlines, reducing interconnection capacitance and enabling high-speed read operations without increasing the planar footprint of the memory cell.
Solution Approach 2:
The patent implements a multi-functional reference layer structure where multiple reference layers serve multiple purposes. The first, second, and third reference layers each form MTJs with the magnetic recording layer, allowing a single memory cell structure to support multiple read operations through shared read bitlines. This universal design enables one structure to perform multiple read functions simultaneously, improving read speed while maintaining compact cell area.
2Area of stationary object
If the memory cell structure is simplified to reduce area, then the memory cell area is reduced, but the read speed decreases due to increased interconnection capacitance
Solution Approach 1:
The patent resolves the area-speed tradeoff by utilizing the vertical dimension. Instead of expanding the planar area to reduce capacitance, the invention stacks reference layers vertically at different heights above and below the magnetic recording layer. This three-dimensional arrangement allows multiple MTJs to share read bitlines, reducing interconnection capacitance and improving read speed while maintaining a compact memory cell footprint.
Solution Approach 2:
The patent employs a nested structure where multiple reference layers are positioned within the vertical space surrounding the magnetic recording layer. The first reference layer is positioned at a first height, the second reference layer at a second height, and the third reference layer at a third height, creating a nested arrangement of MTJs that share read bitlines. This nesting approach reduces interconnection capacitance and improves read speed without increasing the memory cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed read operations while effectively reducing the area required for each memory cell, achieving a smaller footprint compared to traditional designs and enhancing the efficiency of data storage.
Implementation Method 1
achieves data writing by moving the magnetic domain wall through the spin transfer effect of spin-polarized electrons with a write current flown in the in-plane direction of a ferromagnetic film
Implementation Method 2
The electric resistance for a current flown in the direction perpendicular to the film surface of the laminated structure varies depending on the relative angle of the magnetizations of the two ferromagnetic films
Data Source
AI summary
A semiconductor device includes a memory cell. The memory cell includes: a magnetic recording layer formed of ferromagnetic material; first and second magnetization fixed layers coupled to the magnetic recording layer; a plurality of reference layers opposed to the magnetic recording layer; and a plurality of tunnel barrier films respectively inserted between the magnetic recording layer and the reference layers. The first magnetization fixed layer has a magnetization fixed in a first direction, and the second magnetization fixed layer has a magnetization fixed in a second direction opposite to first direction. The reference layers each have a magnetization fixed in the first direction or the second direction. The reference layers and the tunnel barrier layers are positioned between the first and second magnetization fixed layers.