Multi-Reference PLL for DDR2/DDR3 Clock Compatibility
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Solution Overview
Problem
Current phase locked loop systems in FBDIMM memory sub-systems face challenges in supporting multiple generations of DRAM devices and host controllers, particularly due to overlapping operating frequencies, which requires a mechanism to improve jitter budgets and enable simultaneous support of DDR2 and DDR3 memories while maintaining compatibility with both first and second generation host controllers.
Innovation Solution
A multi-reference phase locked loop (MPLL) is developed, which includes a prescaler, reference selector, phase detector, voltage-controlled oscillator, and feedback divider to generate high-speed clocks phase-locked to a lowest common reference frequency derived from multiple reference clocks, allowing for automatic switching between forwarded and system reference clocks to ensure seamless operation across different clocking schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single reference clock is used for all devices in the memory subsystem, then the system clocking scheme remains simple, but the device cannot support both DDR2 and DDR3 memories simultaneously
Solution Approach 1:
The PLL circuit is designed to accept multiple reference clock frequencies (100 MHz for DDR2, 133.33 MHz for DDR3) and automatically configure itself based on the detected reference frequency, enabling a single device to support both DDR2 and DDR3 memory generations without requiring separate clocking circuits for each generation
Solution Approach 2:
The system dynamically adjusts the PLL configuration parameters (prescaler values, divider ratios) based on the detected reference clock frequency, allowing the same hardware to adapt its operating characteristics to match different memory generation requirements
2Reliability
If the reference clock frequency is 24 times lower than the data rate (as in AMB1), then jitter budgets can be controlled, but power consumption is higher and clock recovery is more difficult
Solution Approach 1:
The system dynamically selects between two reference clock frequency ratios: 24:1 for DDR2 (prioritizing jitter control) and 2:1 for DDR3 (prioritizing power reduction and relaxed CDR specifications), with the selection automatically made based on the detected memory generation and reference clock frequency
3Productivity
If a single AMB device supports both DDR2 and DDR3, then product volume increases and cost decreases, but the clocking scheme becomes more complex
Solution Approach 1:
The PLL circuit incorporates universal support for multiple reference clock frequencies and memory generations within a single device architecture, eliminating the need for separate AMB1 and AMB2 devices and enabling a single product to serve both DDR2 and DDR3 markets
Solution Approach 2:
The system performs preliminary detection of the reference clock frequency and automatically configures the PLL parameters before operation begins, allowing the device to seamlessly adapt to different memory generations without requiring complex external configuration or increasing operational complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MPLL enables a single AMB device to simultaneously support both DDR2 and DDR3 memories, reduces power consumption, and maintains compatibility with various host controllers, thereby increasing product volume and market coverage by accommodating overlapping frequencies and ensuring reliable clock recovery.
Implementation Method 1
a phase detector for comparing the selected one of the at least two reference clocks with a feedback clock, and generating a frequency control voltage indicative of a phase error between the compared clocks
Implementation Method 2
a voltage controlled oscillator (VCO) for generating the high speed clock having the high speed clock frequency based on the frequency control voltage until phase locking is indicated by a convergence of the phase error to a substantially constant value
Data Source
AI summary
A multi reference phase locked loop (MPLL) generates a high speed clock frequency and phase locks it to a lowest common reference frequency derived from a selected one of at least two reference clocks. One of the reference clocks is a system reference clock in a FBDIMM system, another may be a forwarded clock in an AMB2. A prescaler reduces the frequency of at least the forwarded clock to the lowest common reference frequency which is the frequency of the system reference clock. A PLL at the core of the MPLL may be locked to the forwarded clock or the system reference clock for generating a high speed clock. A feedback divider generates the feedback clock for the PLL as well as other clocks required in the system. Furthermore, the MPLL provides a number of clocking modes, including modes to facilitate testing and powering down of sections of the circuitry for conserving power.