Multi-Reference PLL Switching Without Loss of Phase Lock
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in achieving high frequency resolution, low jitter, fast response time, tracking large phase errors, and hitless switching without losing lock, especially when switching between reference signals with different frequencies or multiplication factors.
Innovation Solution
A PLL system that includes an oscillator with controllable frequency, multiple time-to-digital converters (TDCs), and a phase error calculation system, allowing for true hitless switching by monitoring and adjusting phase errors to maintain lock, even when switching between reference clocks with different frequencies or multiplication factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL is used, then the circuit is simple, but it cannot track phase errors greater than one reference clock cycle
Solution Approach 1:
The phase error measurement function is segmented into multiple independent TDC channels, each handling a specific reference clock source. This allows the system to track large phase errors from multiple references without requiring a single complex phase detector, resolving the contradiction between tracking capability and circuit complexity.
Solution Approach 2:
The TDC apparatus is designed with multi-functionality to serve multiple reference clock inputs simultaneously. Each TDC channel can independently measure phase errors from different references, and the system universally handles phase errors exceeding one reference cycle through modular architecture, achieving both reliability and manageable complexity.
2Adaptability or versatility
If the PLL switches reference signals, then multiple reference sources are supported, but the PLL may temporarily lose lock due to phase differences
Solution Approach 1:
The system performs preliminary phase error measurement and compensation before switching reference signals. By pre-measuring phase offsets of potential reference clocks and adjusting the output phase accordingly, the PLL maintains continuous lock during switching, achieving both adaptability and reliability.
Solution Approach 2:
Multiple TDC channels continuously provide feedback on phase errors from different reference clocks. This feedback mechanism enables the PLL to predict and compensate for phase differences before switching occurs, ensuring seamless reference signal transitions without losing lock.
3Measurement precision
If integer division is used, then the circuit is simple, but the frequency resolution is low
Solution Approach 1:
The TDC apparatus acts as an intermediary between the phase detector and the frequency synthesizer. By measuring phase errors with high precision and providing detailed feedback, the TDC enables fine frequency resolution without requiring complex fractional division circuits, resolving the contradiction between measurement precision and device complexity.
Data Source
AI summary
A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless.