Multi-Resonant Clock Distribution Network Power Reduction

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Solution Overview

Problem

High-speed clock distribution in integrated circuits leads to significant power dissipation due to the need for low-jitter, high-frequency clock signals being generated from a central phase-locked loop and distributed across the chip, especially in multi-lane architectures, where clocks may be routed over several millimeters, resulting in substantial power consumption.

Innovation Solution

A multi-resonant clock distribution network is created by combining a multi-port electrical network and a transmission line, featuring series inductive reactance and shunt inductive susceptance to produce first and second resonances, generating a bandpass response across a wide range of clock distribution frequencies, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-frequency clock signals are distributed from a central PLL across the integrated circuit, then low-jitter clock signals are provided to critical circuitry, but significant power dissipation occurs due to the long distribution distances

Engineering Contradiction:
Improveclock signal qualityVSAvoidpower dissipation
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The clock distribution network is segmented into multiple resonant stages, each operating at a specific frequency. The first resonant circuit operates at a first frequency while the second resonant circuit operates at a second frequency, dividing the distribution task into frequency-specific segments that reduce overall power dissipation across the integrated circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the operating parameters by using multiple resonant frequencies instead of a single high-frequency clock. The first and second resonant circuits operate at different frequencies, allowing the system to achieve the required clock distribution with lower power consumption by exploiting resonant conditions at multiple frequency points.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If clock distribution frequencies are extended to cover a wider bandwidth, then more flexible clocking options are available, but power dissipation increases due to the need to drive more frequency components

Engineering Contradiction:
Improveclock distribution bandwidthVSAvoidpower dissipation
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent employs resonant circuits that exploit natural vibration frequencies of electrical components. The first and second resonant circuits are designed to resonate at specific frequencies, creating amplified voltage outputs without requiring proportional increases in input power. This resonant vibration approach enables wide bandwidth coverage while maintaining power efficiency.

Inventive Principle:
Principle #18Mechanical vibration

Solution Approach 2:

The clock distribution network is designed with multi-functional resonant circuits that can operate at multiple frequencies. The first resonant circuit and second resonant circuit provide universal clocking capability across different frequency ranges, allowing the same hardware structure to serve multiple frequency requirements without proportionally increasing power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The multi-resonant structure achieves power savings by maintaining high impedance at critical points for optimal power injection and output voltage, extending the bandwidth of clock distribution frequencies and reducing power dissipation across the integrated circuit.

Implementation Method 1

A multi-resonant clock distribution network is created by combining a multi-port electrical network and a transmission line, featuring series inductive reactance and shunt inductive susceptance to produce first and second resonances

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS10606306B2Method of reducing power dissipation in a clock distribution network for integrated circuit
Publication Date: 2020.03.31 MARVELL ASIA PTE LTD
  • US10606306B2 patent drawing
  • US10606306B2 patent drawing
  • US10606306B2 patent drawing

AI summary

A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network. Various implementations are provided, including single-ended, differential, multi-section, multi-output, and point-to-multi-point implementations, each with an optional low-speed mode switch.