Multi-Resonant LC Clock Circuit for Trapezoidal CMOS Drive
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Solution Overview
Problem
Conventional LC oscillators generate sinusoidal clock signals that require additional stages for modification to achieve trapezoidal waveforms necessary for driving CMOS systems, leading to increased power dissipation and phase noise issues in phase-locked loop (PLL) oscillators.
Innovation Solution
A multi-resonant LC network configuration that simultaneously resonates at a fundamental frequency and its third harmonic, generating a trapezoidal clock signal through a combination of resonating signal components with phase-aligned inflection points, reducing the need for additional amplification and buffering stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional LC oscillator generates a sinusoidal clock signal, then the oscillator can operate with a simple circuit configuration, but additional amplification and buffering stages are required to achieve trapezoidal waveforms, leading to increased power dissipation
Solution Approach 1:
The patent combines multiple LC tank circuits with different resonant frequencies (fundamental frequency and third harmonic) into a single integrated oscillator circuit. This merging eliminates the need for separate amplification and buffering stages that would be required to generate trapezoidal waveforms from a simple sinusoidal oscillator, thereby reducing power dissipation while maintaining circuit simplicity.
Solution Approach 2:
The oscillator circuit is designed to simultaneously generate multiple frequency components (fundamental and third harmonic) and directly produce the desired trapezoidal waveform shape. This multi-functionality allows the single circuit to perform what would otherwise require multiple separate stages (sinusoidal generation, harmonic addition, waveform shaping), reducing overall power consumption.
2Shape
If additional amplification and buffering stages are added to convert sinusoidal signals to trapezoidal waveforms, then the desired waveform shape is achieved, but phase noise and jitter increase
Solution Approach 1:
The circuit preliminarily generates the third harmonic component at the oscillator stage itself, before the signal would normally pass through additional amplification and buffering stages. By pre-establishing the harmonic content needed for trapezoidal waveforms at the source, the signal maintains better phase coherence and experiences less phase noise degradation throughout the signal path.
Solution Approach 2:
The patent merges the fundamental frequency and third harmonic generation into a single synchronized oscillator circuit, ensuring both components are generated simultaneously with proper phase alignment. This unified approach prevents the phase noise and jitter that would result from combining signals from separate, independently timed stages.
3Device complexity
If a single-tone continuous waveform is generated, then the oscillator circuit is simple, but the signal cannot directly drive CMOS logic devices with adequate slew rates
Solution Approach 1:
The patent changes the spectral parameters of the generated signal by intentionally incorporating third harmonic content alongside the fundamental frequency. This parameter modification (adding harmonic components) directly improves the slew rate and edge sharpness of the output waveform, enabling direct driving of CMOS logic devices without requiring additional waveform-shaping circuitry.
Solution Approach 2:
The oscillator employs resonant LC tank circuits that naturally generate sinusoidal vibrations at specific frequencies. By configuring multiple resonant circuits with a 3:1 frequency ratio and combining their outputs with proper phase alignment, the system produces a composite waveform with enhanced transient response and slew rate, suitable for direct CMOS driving.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power dissipation and phase noise, enabling direct driving of CMOS logic devices with improved slew rates and reduced jitter, while maintaining efficient power usage by recycling charge within the LC network.
Implementation Method 1
the LC network is configured to simultaneously resonate at a first resonance frequency and a second resonance frequency that is substantially three times the first resonance frequency
Data Source
AI summary
A clock device includes an LC network that has a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.