Multi-Reticle Die Assembly With Reticle-Bridging Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device packaging methods face challenges with increased manufacturing costs and circuit path lengths due to the integration of multi-reticle semiconductor devices, which are limited by lithographic reticle sizes and require additional components like interposers for connectivity.
Innovation Solution
A prefabricated device connection layer is directly bonded to multi-reticle semiconductor devices at a panel level, using reticle-bridging conductors to connect discrete circuit regions and facilitate interconnectivity with other semiconductor devices and external contacts, reducing the need for dedicated interposers and minimizing circuit path lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-reticle semiconductor devices are integrated using conventional packaging methods with interposers, then interconnectivity between discrete circuit regions is achieved, but manufacturing costs increase and circuit path lengths are extended
Solution Approach 1:
The patent extracts and eliminates the interposer component from the conventional packaging architecture. By directly bonding multi-reticle dies to the substrate without an intermediate interposer layer, the solution removes the additional manufacturing steps, materials, and alignment requirements that interposers introduce, thereby reducing manufacturing costs while maintaining electrical connectivity through direct die-substrate bonding
Solution Approach 2:
The patent applies preliminary action by pre-forming bond pads and conductive structures on the substrate before bonding the multi-reticle dies. This advance preparation enables direct electrical connectivity to be established during the bonding process itself, eliminating the need for subsequent interposer fabrication and assembly steps, thus reducing overall manufacturing complexity and cost
2Reliability
If multi-reticle semiconductor devices are integrated using conventional packaging methods with interposers, then interconnectivity between discrete circuit regions is achieved, but circuit path lengths are extended
Solution Approach 1:
The patent removes the interposer layer that physically extends the distance between bond pads and circuit regions. By bonding dies directly to the substrate, the electrical signal path is shortened as it no longer needs to traverse through the interposer thickness, reducing overall circuit path length and signal delay while maintaining reliable interconnectivity
3Productivity
If lithographic reticle sizes are increased to accommodate larger devices, then device integration density improves, but manufacturing precision deteriorates
Solution Approach 1:
The patent segments the device into multiple smaller reticle-sized dies that are bonded together in a modular fashion. Each die maintains the precise alignment and feature dimensions achievable with standard reticle sizes, while the overall integrated device achieves higher effective density through the multi-die arrangement. This segmentation approach avoids the alignment precision deterioration that would result from attempting to pattern a single large device beyond reticle capabilities
Solution Approach 2:
The patent transitions from a planar integration approach (trying to fit more features on a single large reticle) to a three-dimensional modular architecture where multiple standard-sized dies are stacked or arranged in arrays. This dimensional change allows high integration density to be achieved through vertical stacking or compact 2D arrays of precisely manufactured individual dies, rather than attempting to increase the lateral dimensions of a single reticle pattern
Data Source
AI summary
A semiconductor device assembly comprises an RDL including an external surface with external contacts, an internal surface with internal contacts, and conductors coupling the internal contacts to the external contacts. The assembly further includes a device connection layer having a first surface with first contact pads, a second surface with second contact pads, first conductive structures electrically coupling each of the first contact pads to a corresponding second contact pad, and a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads. The assembly further includes stacks of semiconductor devices disposed between the RDL and the device connection layer, each stack in a cavity in a monolithic glass structure. The stacks electrically couple internal contacts to the first contact pads through TSVs in the stacks.