Multi-Reticle Interposer Layout for High Core Count Die Packaging
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Solution Overview
Problem
High core count compute and graphics devices in HPC platforms face challenges with large die complexes exceeding standard reticle size limits, leading to high costs and performance degradation due to the need for precise alignment and bandwidth issues in existing interposer solutions.
Innovation Solution
The use of interposers with a multiple reticle form factor, featuring saw streets between reticle regions to increase alignment tolerance and reduce costs, allowing for larger form factors without the need for precise alignment and maintaining high-density routing between compute dies and SoCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple exposure solutions (reticle stitching) are used to fabricate interposers larger than reticle size limit, then larger form factor interposers can be manufactured, but manufacturing cost increases due to requirement for precise alignment
Solution Approach 1:
The interposer is divided into multiple separate interposer substrates, each within the reticle size limit. These substrates are then joined together using embedded bridge architectures to form a larger functional interposer structure, eliminating the need for expensive multiple exposure processes while achieving the required large footprint.
2Area of stationary object
If embedded bridge architectures are used to join interposer substrates, then interposers can be constructed from smaller substrates, but bandwidth degradation occurs due to fan-out and fan-in routing requirements
Solution Approach 1:
The signal routing function is extracted from the embedded bridge architecture and relocated to the package substrate level. High-speed signals are routed directly on the package substrate, bypassing the embedded bridges, thereby maintaining bandwidth performance while still allowing the interposer to be constructed from smaller substrates.
3Area of stationary object
If embedded bridge architectures are used to join interposer substrates, then interposers can be constructed from smaller substrates, but power consumption increases due to increased frequency requirements for maintaining bandwidth
Solution Approach 1:
The high-frequency signal transmission function is extracted from the interposer level and moved to the package substrate level. This eliminates the need to increase wire frequency to maintain bandwidth, thereby reducing power consumption while still enabling construction from smaller substrates.
4Area of stationary object
If die is split into two halves with each half sitting above an interposer, then large die complexes can be accommodated, but latency increases due to increased interconnect length for pitch translation
Solution Approach 1:
The interconnect routing is moved from the vertical dimension (through embedded bridges between interposers) to the horizontal dimension (on the package substrate). This dimensional shift reduces the effective path length for signal transmission, thereby reducing latency while still accommodating large die complexes through the multi-substrate interposer construction.
Data Source
AI summary
Embodiments disclosed herein include a multi-die module. In an embodiment, the multi-die module comprises an interposer, where the interposer comprises a first region and a second region. In an embodiment, the first region is spaced apart from the second region by a saw street. In an embodiment, a first die is over the interposer, where the first die is positioned over the saw street. In an embodiment, a second die is adjacent to a first end of the first die, and a third die is adjacent to a second end of the first die opposite from the first end.