Multi-role PCH as IO Expander for Reduced Die Real Estate
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Solution Overview
Problem
The increasing internal clock frequencies of CPUs lead to performance bottlenecks in traditional Northbridge-Southbridge architectures, prompting the integration of Northbridge functions into System-on-Chip (SoC) processor architectures, where the Southbridge is replaced by the Platform Controller Hub (PCH), but existing PCH features like boot control, high-speed IOs, and manageability are still valued, necessitating a dynamic and configurable PCH solution.
Innovation Solution
A multi-role PCH that can be configured to operate as either a legacy PCH for boot functionality or as an IO-expander to expand IO interfaces, using deterministic firmware and handshake signals to coordinate with other PCHs, allowing it to serve both roles with the same device, thereby reducing real estate usage and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PCH features are integrated into SoC processor architecture, then processor performance is improved, but processor die real estate is consumed
Solution Approach 1:
The PCH functionality is segmented from the SoC processor and implemented as a separate IO expander device. This segmentation allows the processor to focus on computational functions while the separate PCH device handles IO control functions, thereby improving processor performance without consuming additional processor die real estate.
Solution Approach 2:
The PCH device is designed with multi-functionality to perform both traditional PCH roles (boot control, IO management) and new IO expander functions. This universal design allows a single device to replace multiple separate components, achieving the desired functionality without proportionally increasing die real estate consumption.
2Adaptability or versatility
If multiple PCH devices are used in multi-socketed architectures, then IO functionality is expanded, but processor die real estate and system complexity increase
Solution Approach 1:
Each PCH device in the multi-socketed architecture is designed as a universal IO expander that can function independently or in coordination with other PCH devices. This multi-functional design allows the same device type to be used across multiple sockets, expanding IO functionality while maintaining consistent device architecture and reducing overall system complexity.
Solution Approach 2:
The PCH devices serve as intermediary components between the processor and various IO devices. By positioning PCH devices as mediators that handle IO protocol conversion and management, the system achieves expanded IO functionality while isolating the processor from complex IO control logic, thereby reducing system complexity.
3Loss of substance
If PCH is configured as IO-expander, then Bill of Material costs are reduced, but boot control functionality must be handled by CPU
Solution Approach 1:
The boot control functionality is extracted from the traditional PCH device and transferred to the CPU. This extraction allows the PCH device to be simplified as an IO expander with reduced functionality, enabling the use of lower-cost PCH devices while the CPU assumes the boot control responsibilities. This reduces overall Bill of Material costs by allowing the use of more cost-effective components in the PCH device.
Data Source
AI summary
Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH. The multi-socket platforms include a platform with a bootable CPU coupled to one or more non-legacy CPUs and employing multiple IO-expanders and platform with a legacy CPU coupled to one or more non-legacy CPUs and coupled to a legacy PCH, and further including one or more PCHs coupled to the non-legacy CPU(s) implemented as IO-expanders.