Multi-ROM Finite State Machine Circuit Design
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Solution Overview
Problem
Existing electronic systems implementing programmable functionality, such as microcontrollers and field programmable gate arrays, are large, costly, and power-intensive.
Innovation Solution
A multi-read only memory (ROM) state machine circuit comprising first and second ROMs, with a comparator circuit that compares input bits to determine next state identifiers, allowing efficient state transitions using clock signals to address rows in the ROMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If microcontrollers or field programmable gate arrays are used to implement programmable functionality, then the system can perform complex operations, but the device size, cost, and power consumption increase significantly
Solution Approach 1:
The patent divides the state machine functionality into multiple ROMs, each handling specific aspects of state management. Instead of using a single large programmable device, the system segments the functionality across several smaller, simpler ROM components that work together to achieve the desired programmable behavior with reduced power consumption and device size.
Solution Approach 2:
The patent uses ROMs to store and copy state machine logic and data rather than implementing complex programmable logic circuits. By copying the necessary state information and transition logic into ROM memory structures, the system achieves programmable functionality through simple, power-efficient memory access operations instead of power-hungry programmable logic.
2Adaptability or versatility
If microcontrollers or field programmable gate arrays are used to implement programmable functionality, then the system can perform complex operations, but the device size and cost increase significantly
Solution Approach 1:
The patent divides the state machine functionality into multiple ROMs, each handling specific aspects of state management. Instead of using a single large programmable device, the system segments the functionality across several smaller, simpler ROM components that work together to achieve the desired programmable behavior with reduced device size.
Solution Approach 2:
The patent uses ROMs to store and copy state machine logic and data rather than implementing complex programmable logic circuits. By copying the necessary state information and transition logic into ROM memory structures, the system achieves programmable functionality through simple, space-efficient memory access operations instead of space-hungry programmable logic.
3Adaptability or versatility
If microcontrollers or field programmable gate arrays are used to implement programmable functionality, then the system can perform complex operations, but the cost increases significantly
Solution Approach 1:
The patent divides the state machine functionality into multiple ROMs, each handling specific aspects of state management. Instead of using a single large programmable device, the system segments the functionality across several smaller, simpler ROM components that work together to achieve the desired programmable behavior with reduced cost.
Solution Approach 2:
The patent uses ROMs to store and copy state machine logic and data rather than implementing complex programmable logic circuits. By copying the necessary state information and transition logic into ROM memory structures, the system achieves programmable functionality through simple, cost-effective memory access operations instead of expensive programmable logic implementation.
4Use of energy by moving object
If multiple ROMs are used to implement the state machine circuit, then power consumption and device size are reduced, but the device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple ROMs with a comparator circuit and register into a unified state machine system. By combining these components into a coordinated workflow where ROMs store state information, the comparator evaluates transitions, and the register holds current state, the system achieves power efficiency without managing excessive complexity through integrated component interaction.
Solution Approach 2:
The patent introduces a comparator circuit as an intermediary between the ROMs and the state transition logic. This intermediary component simplifies the overall system by handling the complex comparison operations externally, allowing the ROMs themselves to remain simple memory structures while still achieving sophisticated state machine functionality through the mediating comparator.
Data Source
AI summary
A multi-read only memory (ROM) state machine circuit includes first and second ROMs (or other memory types), each ROM addressable as a plurality of rows. Each row of the first ROM includes a pointer. Each row of the second ROM includes a set of input compare bits and a next state identifier. A comparator circuit compares each input bit to the state machine circuit to a corresponding bit of the set of input compare bits from the second ROM. A register stores next state identifiers from the second ROM based on the comparator's outputs. Upon receipt of a clock edge, the stored next state identifier from the register is used an address to read a row from the first ROM. The pointer from the first ROM row is then used as an address to read a row from the second ROM. Responsive to the comparator circuit, the next state identifier corresponding to a set of input compare bits that match the input bits to the finite state machine circuit is stored in the register and used as an address to read another row from the first ROM.