Multi-Root NIC Architecture for NUMA DMA Without Software Overhead
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Solution Overview
Problem
Existing network interface controllers (NICs) with multiple bus interfaces for NUMA systems face performance bottlenecks due to asymmetrical memory access and complex software overhead from managing multiple devices, which impede efficient data transfer and peer-to-peer transactions.
Innovation Solution
A NIC with multiple connections to a server exposes only a single connection to the host operating system as a network communication device, utilizing separate DMA engines for additional connections to manage resources efficiently, segregating network and DMA functions to avoid bottlenecks and enhance data transfer speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple bus interfaces are used for NUMA systems, then memory access speed is improved, but device complexity increases
Solution Approach 1:
The patent divides the single network device into multiple virtual functions, where each virtual function can be associated with different bus interfaces. This segmentation allows the device to leverage multiple PCIe roots for parallel memory access while presenting a unified interface to the host, thus improving speed without proportionally increasing complexity.
Solution Approach 2:
The network device is designed to perform multiple functions through a single unified interface. It can handle network communication, DMA operations, and memory access through different virtual functions all exposed through one bus interface, reducing the need for multiple separate devices while maintaining high-speed access capabilities.
2Productivity
If multiple bus interfaces are used for NUMA systems, then data transfer efficiency is improved, but software overhead increases
Solution Approach 1:
The patent merges multiple bus interface operations into a single unified interface. By combining the functionality of multiple PCIe roots into one interface with multiple virtual functions, it simplifies software management while maintaining the data transfer efficiency benefits of multi-interface architecture.
Solution Approach 2:
The unified interface acts as an intermediary between the host and multiple bus interfaces. It manages the complexity of coordinating multiple PCIe roots and memory access paths, presenting a simplified interface to software while handling the complex coordination internally, thus improving data transfer efficiency without increasing software overhead.
3Adaptability or versatility
If network and DMA functions are combined, then device versatility is improved, but resource contention occurs
Solution Approach 1:
The patent segments network and DMA functions into separate virtual functions within the unified interface. This allows independent resource allocation and management for each function, preventing resource contention while maintaining device versatility. Each virtual function can be independently configured and managed.
Solution Approach 2:
The unified interface dynamically allocates and manages resources between network and DMA functions based on current needs. It can adjust resource distribution in real-time, allowing the device to be versatile while avoiding resource contention through dynamic resource management rather than static allocation.
Data Source
AI summary
Network communication apparatus for connection to a computer that includes a host processor, a host memory and at least first and second root ports. The apparatus includes a network port, for connection to a packet communication network, and first and second host bus interfaces, for connection via respective first and second peripheral component buses to the first and second root ports, respectively. Packet processing logic is coupled between the network port and the first and second host bus interfaces and includes first and second direct memory access (DMA) engines to read data from the host memory via the first and second root ports, respectively, for transmission via the network port, while exposing the network port to the host computer only through the first host bus interface.