Dynamic Multi-Root NoC Routing for Flexible IC Test Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit (IC) devices face challenges in functional and scan testing due to the need for dedicated circuitry and communication paths specific to the test type, which are not reusable beyond their designated purpose, and many IC devices lack sufficient programmable logic to configure for testing.
Innovation Solution
A multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation, featuring a dynamically configurable bus network with multi-port switch circuits and fixed links, allowing flexible communication paths and protocol handling for various testing and debugging purposes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated circuitry and communication paths are designed for specific test types, then testing reliability is improved, but device complexity and resource usage increase
Solution Approach 1:
The patent implements a universal bus network that can be dynamically reconfigured to support multiple test types (scan testing, functional testing, debugging) through a single infrastructure. The multi-port switch circuits and configurable communication paths allow the same hardware to serve different testing purposes, eliminating the need for separate dedicated circuitry for each test type while maintaining testing reliability
Solution Approach 2:
The patent employs dynamically reconfigurable communication paths that can be adjusted during operation to accommodate different test requirements. The bus network topology and routing can be changed on-the-fly to establish appropriate test configurations, allowing the system to adapt to various testing scenarios without requiring static dedicated paths for each test type
2Measurement precision
If dedicated circuitry is designed for specific test types, then measurement precision is improved, but loss of substance increases
Solution Approach 1:
The bus network infrastructure serves multiple testing and debugging functions through dynamic reconfiguration, allowing the same physical resources to be reused across different test types. This eliminates waste of programmable logic resources while maintaining the precision needed for different measurement and testing operations through appropriate configuration
3Adaptability or versatility
If FPGA fabric is used for testing, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent introduces multi-port switch circuits as intermediary components that manage the complexity of reconfiguration. These switches act as mediators between the programmable logic and the communication infrastructure, handling the dynamic routing and configuration tasks that would otherwise require complex FPGA programming, thereby reducing the burden on the FPGA fabric while maintaining high adaptability
Data Source
AI summary
Embodiments herein describe an integrated circuit (IC) device that includes a multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation (DFxNoC). A DFxNoC may include a plurality of end-points (EPs) that include functional circuitry, first and second root devices, and a bus network that includes multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the root devices, and the EPs, where the root devices output respective first and second clocks, and where the multi-port switch circuits are dynamically configurable to route the first and second clocks to respective first and second selectable sets of one or more of the EPs over the network of fixed links.