Multi-Root Reset Handling via Sideband Interface
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Solution Overview
Problem
The integration of diverse intellectual property blocks into a single system-on-chip (SoC) is complex due to varying requirements and design uniqueness, leading to slow design emergence and increased complexity, especially in multi-root systems where independent reset and resource management are challenging.
Innovation Solution
The implementation of a standardized on-die interconnect protocol, such as the Integrated On-Chip System Fabric (IOSF) specification, which enables efficient communication and resource management across IP blocks, allowing for multiple root spaces and independent reset domains within a shared fabric, facilitating the integration of diverse IP blocks and reducing design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If diverse IP blocks are integrated into a single SoC, then functionality and versatility are improved, but design complexity increases
Solution Approach 1:
The system is divided into multiple independent root spaces, each capable of being reset independently. This segmentation allows different IP blocks to be organized into separate root spaces with their own reset domains, enabling granular control over reset operations and reducing the complexity of managing diverse IP blocks in a single integrated system.
Solution Approach 2:
The reset mechanism is designed to be universal across multiple root spaces and IP blocks. A single reset controller can issue reset signals to multiple root spaces, and each root space can contain multiple IP blocks. This multi-functional design allows the same reset infrastructure to serve diverse IP blocks, reducing overall design complexity while maintaining versatility.
2Reliability
If independent reset domains are implemented for each IP block, then reliability and controllability are improved, but device complexity increases
Solution Approach 1:
Multiple reset domains are merged into a unified root space architecture where root spaces can contain multiple IP blocks. The reset controller manages multiple root spaces through a standardized interface, and root spaces share common infrastructure such as the fabric and reset controller. This merging approach provides independent reset control for reliability while reducing system complexity through resource sharing.
Solution Approach 2:
The root space acts as an intermediary layer between the reset controller and individual IP blocks. The reset controller issues reset signals to root spaces, which then manage the reset distribution to their contained IP blocks. This intermediary structure provides centralized control for reliability while simplifying the interface between the reset controller and diverse IP blocks, reducing overall system complexity.
3Adaptability or versatility
If multiple root spaces are supported in a shared fabric, then adaptability and resource management are improved, but manufacturing complexity increases
Solution Approach 1:
The system employs homogeneous root space structures with standardized interfaces and reset mechanisms. Each root space follows the same architectural pattern, allowing for systematic design and easier manufacturing. The uniform structure of root spaces, despite containing diverse IP blocks, enables standardized manufacturing processes and faster design emergence while maintaining high adaptability for multi-root operations.
Data Source
AI summary
In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.