Multi-Root Semiconductor Fabric for IP Integration
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Solution Overview
Problem
The integration of diverse intellectual property (IP) blocks into a single system-on-chip (SoC) is hindered by design complexity and customization requirements, necessitating re-design to accommodate varying interface and signaling needs, which slows the development of advanced semiconductor devices.
Innovation Solution
The implementation of a standardized on-die interconnect protocol, such as the Integrated On-Chip System Fabric (IOSF) specification, enables efficient integration of IP blocks by defining interfaces, protocols, and arbitration mechanisms, allowing for broad use across different types of chips and facilitating design reuse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IP blocks are customized to accommodate varying interface and signaling requirements of different SoC segments, then adaptability to different markets is improved, but device complexity and design time increase significantly
Solution Approach 1:
The patent implements a universal root complex design that can operate in multiple root space configurations (single-root and multi-root modes) without requiring separate customized designs for each market segment. The root complex includes configurable components such as the address decoder and arbitration logic that can be programmed to support different SoC architectures, thereby achieving adaptability across server, desktop, mobile, and embedded markets while maintaining a single standardized design
2Manufacturing precision
If IP blocks are re-designed for each SoC to meet specific interface requirements, then integration accuracy is improved, but productivity and development speed decrease
Solution Approach 1:
The patent performs preliminary configuration of the root complex components during system initialization rather than requiring redesign for each integration. The address decoder and arbitration mechanisms are pre-designed with configurable parameters that are programmed according to the specific SoC requirements, allowing rapid adaptation while maintaining integration accuracy through predefined configuration sequences
3Adaptability or versatility
If multiple root spaces are implemented in a single semiconductor device, then adaptability to different market segments is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic root space configuration where the root complex can be programmed to operate in either single-root or multi-root mode based on the specific market segment requirements. The arbitration logic and address decoding mechanisms are designed to be dynamically reconfigurable through programming, allowing the same hardware structure to adapt to different root space configurations without requiring physical redesign or increasing inherent structural complexity
Data Source
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AI summary
In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.