Multi-Row Current Calibration for Nonvolatile CIM Memory
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Solution Overview
Problem
Conventional non-volatile computing-in-memory (CIM) technologies face challenges in achieving high bandwidth and low power consumption due to the close resistance states of neighboring memory cells, limiting the accuracy of accumulation results and increasing power consumption when multiple word lines are activated.
Innovation Solution
A memory unit with multiple word lines and a multi-row current calibration circuit that generates a calibration current to subtract from the bit-line current, enabling calibration and reducing errors caused by high and low resistance states, thereby increasing throughput and signal margin while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple word lines are activated simultaneously to increase bandwidth and reduce power consumption, then throughput is improved, but the accumulation result on the bit line is highly affected by the R-ratio of NVM devices causing increased error rate
Solution Approach 1:
The patent creates a replica memory array that copies the structure and state of the main memory array. This replica array generates a calibration current that mirrors the leakage currents from high resistance state cells in the main array, enabling accurate calibration without disrupting the primary computation function.
Solution Approach 2:
The patent dynamically adjusts the calibration current parameter based on the actual leakage currents measured from the replica array. By changing the calibration current magnitude to match the leakage profile, the system compensates for R-ratio variations and maintains accurate accumulation results even when multiple word lines are activated.
2Measurement precision
If conventional real-time CIM current calibration technology is used with a single word line, then one-bit HRS and LRS prediction is achieved, but memory bandwidth is greatly limited and average power consumption for reading single memory cell increases
Solution Approach 1:
The patent segments the calibration function into multiple parallel calibration circuits, each handling a specific word line or group of word lines. This segmentation allows simultaneous calibration across multiple word lines, enabling multi-bit prediction while maintaining precision and significantly increasing memory bandwidth compared to sequential single-word-line calibration.
3Productivity
If another conventional calibration technology turns on multiple word lines for non-real-time memory calculation, then integration of charge is performed, but extra time is taken to eliminate interference information and throughput is reduced
Solution Approach 1:
The patent performs calibration actions preliminarily by generating the calibration current from the replica array in parallel with the main computation. The calibration current is prepared and available before the actual read operation completes, eliminating the need for post-computation interference elimination and avoiding cycle time extension.
Solution Approach 2:
The replica array continuously generates calibration current throughout the computation process, maintaining a steady calibration signal that can be immediately used for accurate read operations. This continuous calibration action eliminates idle time and ensures that useful computation and calibration proceed simultaneously without interruption or cycle extension.
4Reliability
If another conventional calibration technology uses high-impedance storage unit to eliminate accumulated charge, then interference information is removed, but implementation is limited to voltage signals and cannot be directly used by next level circuit in current form
Solution Approach 1:
The patent replaces the voltage-based high-impedance storage unit mechanism with a direct current-based calibration approach. Instead of converting currents to voltages for calibration and then converting back, the system maintains calibration in the current domain throughout, making the output directly compatible with current-mode next level circuits and eliminating signal type conversion limitations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for simultaneous activation of multiple word lines, enhancing throughput and achieving larger signal margins with reduced power and area overhead, effectively addressing the limitations of conventional CIM technologies.
Implementation Method 1
Each of the non-volatile memory cells is in one of a high resistance state and a low resistance state, and the bit-line current is equal to a sum of the memory cell currents
Implementation Method 2
Each of the replica non-volatile memory cells is in the high resistance state, and the calibration current is equal to a sum of the replica memory cell currents
Implementation Method 3
The multi-row current calibration circuit is configured to subtract the calibration current from the bit-line current to generate a calibrated dataline current
Data Source
AI summary
A memory unit with multiple word lines for a plurality of non-volatile computing-in-memory applications is configured to compute a plurality of input signals and a plurality of weights. The memory unit includes a non-volatile memory cell array, a replica non-volatile memory cell array and a multi-row current calibration circuit. The non-volatile memory cell array is configured to generate a bit-line current. The replica non-volatile memory cell array includes a plurality of replica non-volatile memory cells and is configured to generate a calibration current. Each of the replica non-volatile memory cells is in the high resistance state. The multi-row current calibration circuit is electrically connected to the non-volatile memory cell array and the replica non-volatile memory cell array. The multi-row current calibration circuit is configured to subtract the calibration current from a dataline current to generate a calibrated dataline current. The dataline current is equal to the bit-line current.