Multi-Row Physical Layer Interface for IC Package Signal Integrity
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Solution Overview
Problem
Conventional IC chip designs face challenges in reducing chip size while maintaining effective signal transmission due to the arrangement of physical layer interfaces in a single row, which affects transmission quality and increases the length of redistribution lines, leading to signal decay.
Innovation Solution
The IC package features a physical layer interface arrangement with multiple rows of bump pads and inner pads, arranged in a mirror-symmetric manner, which reduces the length of redistribution lines and expands the usable signal area, allowing for improved signal transmission and chip size reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If physical layer interfaces are arranged in a single row, then the chip area is reduced, but the signal transmission quality deteriorates due to increased redistribution line length
Solution Approach 1:
The patent transitions from a single-row arrangement to a multi-row arrangement of physical layer interfaces. By adding the dimensional aspect of multiple rows, the design achieves both area efficiency and signal quality. The inner pads are distributed across multiple rows, allowing shorter redistribution lines while maintaining compact chip area.
2Adaptability or versatility
If the number of bump pads is increased to support more functions, then the signal transmission capability is improved, but the chip area increases
Solution Approach 1:
The patent implements a nested structure where inner pads are positioned within the signal area and connected to bump pads through redistribution lines. This nesting allows multiple functional interfaces to be integrated in a compact arrangement, supporting increased signal transmission capability without proportionally increasing chip area.
3Area of stationary object
If the dimensions of patterned metal layers are reduced, then the chip area is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent segments the signal transmission path into distinct components: bump pads, redistribution lines, and inner pads arranged in multiple rows. This segmentation allows each component to be optimized independently, enabling reduced overall dimensions while maintaining manufacturability through standardized design rules for each segment.
Data Source
AI summary
An integrated circuit (IC) package includes an IC chip, a package carrier, and a plurality of conductive bumps connecting the IC chip to the package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The active surface has a core area and a signal area surrounding the core area. The IC layered structure includes a first physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The first inner pads are arranged in multiple rows in the signal area.