Multi-Row SRPG Cell Layout for Lower Routing Congestion
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Solution Overview
Problem
Current State Retention Power Gated (SRPG) cells in integrated circuits face high routing congestion and low utilization of Sea of Gates (SOG) due to excessive routing resources used by the secondary power supply VDDC, leading to increased die size and high well-leakage in standby mode.
Innovation Solution
A multi-row height layout for SRPG cells is implemented, where semiconductor devices are arranged across multiple rows with separate power supply lines for each row, reducing metal routing resources and minimizing N-wells tied to VDDC, thereby enhancing SOG utilization and reducing well-leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single-row-height SRPG cell is used, then the cell layout is compact, but routing congestion increases and SOG utilization decreases
Solution Approach 1:
The patent transitions from a single-row-height layout to a multi-row-height layout, adding the vertical dimension to the cell structure. This dimensional change allows power routing to be distributed across multiple rows, reducing horizontal routing congestion and improving Sea of Gates utilization while maintaining compact cell area.
2Reliability
If VDDC power supply is used to retain state in standby mode, then state retention is achieved, but well-leakage increases due to continuously powered circuitry
Solution Approach 1:
The patent segments the power supply network into multiple independent VDDC power supply lines, each serving specific rows or regions of the circuit. This segmentation allows selective powering of only the necessary circuitry required for state retention, while other segments can be powered down, thereby reducing well-leakage while maintaining state retention capability.
3Reliability
If excessive VDDC routing resources are used, then state retention is ensured, but die size increases
Solution Approach 1:
The patent applies local quality by providing VDDC power supply lines only to the specific rows containing circuitry that requires state retention in standby mode. Rather than uniformly powering all rows, the power routing is localized to where it is actually needed, reducing overall routing resource consumption and minimizing die size while ensuring reliable state retention.
Data Source
AI summary
A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.