Multi-Sampling PLL Frequency Generator for Lower Phase Noise

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Solution Overview

Problem

Current phase-locked loop (PLL) systems for voltage controlled oscillators (VCOs) face challenges in achieving improved phase noise response due to noise contributions from reference oscillators, VCOs, and loop components, which affect the stability and accuracy of the output signal.

Innovation Solution

A phase-locked loop configuration that includes multiple sampling phase detectors, a phase and frequency detector, a loop integrator, a power detector, and offset voltage generators to adjust bias voltages, enhancing the coherence and signal-to-noise ratio of the combined beat signal and thereby reducing phase noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple sampling phase detectors are used to improve signal-to-noise ratio, then phase noise is reduced, but device complexity increases

Engineering Contradiction:
Improvephase noise performanceVSAvoidnumber of sampling phase detectors
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple sampling phase detectors are combined in parallel configuration, where each detector processes the same VCO output signal but with different sampling phases. The outputs of these detectors are summed together to produce a combined beat signal with improved signal-to-noise ratio. This merging approach reduces phase noise by averaging out random noise components while preserving the coherent signal components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The phase detection function is segmented into multiple parallel sampling phase detectors, each operating at different sampling phases (e.g., 0°, 90°, 180°, 270°). This segmentation allows the system to capture the VCO output signal at multiple points in its cycle, and through coherent summation, reconstruct a more accurate representation of the original signal with reduced noise impact.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple sampling phase detectors are used to improve phase noise, then manufacturing cost increases

Engineering Contradiction:
Improvephase noise performanceVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The sampling phase detectors are designed with universal functionality to process the same type of input signal (VCO output) and produce comparable output formats (beat signals). This uniformity allows for standardized manufacturing processes and component selection, reducing the overall manufacturing complexity and cost despite the increased number of detectors. The modular design enables easier integration and testing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If multiple sampling phase detectors are used to improve signal-to-noise ratio, then the combined noise floor of loop components increases

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidcombined noise floor
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the potentially harmful effect of multiple noise sources into a beneficial outcome by utilizing coherent summation. While each sampling phase detector introduces its own noise, the coherent addition of signal components across multiple detectors causes the signal power to increase proportionally to N², while incoherent noise power increases only proportionally to N. This results in an improved signal-to-noise ratio of 10*log10(N) dB, effectively converting the presence of multiple noisy components into a performance advantage.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS7940130B2Frequency generator and method of frequency generation with multiple sampling phase detectors
Publication Date: 2011.05.10 KEYSIGHT TECHNOLOGIES INC
  • US7940130B2 patent drawing
  • US7940130B2 patent drawing
  • US7940130B2 patent drawing

AI summary

A device includes: a plurality of sampling phase detectors, each receiving a sampling signal and a VCO output signal and in response thereto outputting a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a frequency/phase detector receiving a reference signal and a combined beat signal produced by combining the beat signals, and in response thereto producing an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator receiving the error signal and in response thereto producing the VCO control signal; a power detector detecting a power level of the combined beat signal; and at least one offset voltage generator adjusting a value of a bias voltage in response to the detected power level of the combined beat signal, and applying the adjusted bias voltage to one of the sampling phase detectors.