Multi-Segment Spacer Structures for Multi-Gate Transistor Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in enhancing the reliability and operation characteristics of multi-gate transistors due to the limitations of current spacer structures, which affect the scalability and short channel effect suppression.
Innovation Solution
The implementation of a semiconductor device design that includes a field insulating layer, gate structures, and spacer structures formed on the sidewalls and lower surfaces of the gate electrodes, with additional spacer structures on the upper surface of the insulating layer, to improve current control and suppress short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional spacer structures are used in multi-gate transistors, then the device structure is simpler, but the reliability and operation characteristics deteriorate due to poor current control and short channel effects
Solution Approach 1:
The spacer structure is divided into multiple segments: a first spacer on the sidewall of the gate electrode, a second spacer on the lower surface of the gate electrode, and a third spacer on the field insulating layer. This segmentation allows each spacer to perform specific functions for current control and short channel effect suppression, thereby improving reliability without requiring a completely new complex structure
Solution Approach 2:
The spacer structure extends from conventional two-dimensional planar spacers into three-dimensional multi-layer configuration. The spacers are formed at different heights and positions (sidewall, lower surface, and field insulating layer), creating a vertical stacking arrangement that provides enhanced control over the channel region and effectively suppresses short channel effects
2Reliability
If the gate length is increased to improve current control, then current control capability improves, but the scalability of the transistor deteriorates
Solution Approach 1:
The invention transitions from controlling current through gate length (one-dimensional parameter) to controlling current through multi-dimensional spacer structures. The spacers extend vertically and laterally to form a three-dimensional configuration that controls the channel without requiring increased gate length, thereby maintaining scalability while improving current control
Solution Approach 2:
The spacer structures act as intermediary elements between the gate electrode and the channel region. These spacers provide an additional control mechanism that mediates the electric field distribution and carrier flow, enabling improved current control without directly increasing the gate length
3Reliability
If conventional spacer structures are used, then the manufacturing process is simpler, but short channel effects are not effectively suppressed
Solution Approach 1:
The spacer formation process is segmented into multiple steps corresponding to different spacer positions and functions. Each spacer (first, second, and third) can be formed using standard semiconductor fabrication techniques applied at different stages, allowing the complex three-dimensional structure to be manufactured using conventional process building blocks
Solution Approach 2:
The spacer structures are formed in advance before final device assembly and operation. The multi-layer spacer configuration is established during the fabrication process, preparing the structure to automatically provide short channel effect suppression and current control during device operation without requiring additional complex post-processing steps
Data Source
AI summary
Semiconductor devices may include a field insulating layer that is on a substrate, a gate structure that is on the substrate and separated from the field insulating layer, a first spacer structure that is on sidewalls and a lower surface of the gate structure and is separated from the field insulating layer, and a second spacer structure that is on a part of an upper surface of the field insulating layer that is overlapped by the gate structure.