Multi-segmented link lines for non-display area reduction
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Solution Overview
Problem
In non-rectangular display panels, the size of the non-display area is increased due to the need for link lines that supply start pulses, shift clocks, and driving voltages to gate drivers, and the embedded gate driver structure is enlarged, making it difficult to minimize this area effectively.
Innovation Solution
A display panel design featuring a curved boundary with multi-segmented link lines that connect gate blocks to pixel rows, including a dummy block, and a layout where the number of gate lines in one area is greater than in another, allowing for a more efficient connection and reduced non-display area size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If link lines are provided in a straight-line shape to connect gate driver to gate lines, then connection is simplified, but the size of the non-display area increases
Solution Approach 1:
The link lines are divided into multiple segments (first link line, second link line, third link line) instead of using a single straight-line connection. This segmentation allows the link lines to be arranged in a stepped pattern that reduces the overall width of the non-display area while maintaining functional connectivity between the gate driver and gate lines.
Solution Approach 2:
The link lines extend in multiple directions (first direction, second direction, third direction) rather than solely in one dimension. This multi-directional arrangement transforms the connection structure from a single-dimensional straight line to a two-dimensional stepped pattern, enabling space optimization in the non-display area.
2Device complexity
If GIP circuit is embedded in the display panel, then the number of link lines is decreased, but the GIP circuit is enlarged in left-to-right direction
Solution Approach 1:
The GIP circuit is divided into multiple gate blocks (first gate block, second gate block, third gate block) arranged in sequence. This segmentation allows the circuit to be distributed across the display panel in a compact manner, reducing the left-to-right dimension while maintaining all necessary functional connections through the segmented link line structure.
Solution Approach 2:
The gate blocks and their corresponding link lines are arranged in a multi-directional stepped pattern rather than a linear left-to-right sequence. This spatial reorganization in multiple dimensions reduces the horizontal footprint of the GIP circuit while preserving all functional connections.
3Reliability
If multiple link lines extend from gate line in non-rectangular display panel, then all gate lines are connected, but the non-display area increases
Solution Approach 1:
The link lines are segmented into multiple sections (first, second, third link lines) that connect to different gate lines at different positions. This segmentation enables each link line to serve multiple connection functions, ensuring all gate lines are connected while minimizing the overall space required in the non-display area.
Solution Approach 2:
Each link line is designed to connect multiple gate lines (first gate line, second gate line, third gate line, etc.) through its segmented structure. This multi-functional design allows a single link line to perform the connection function for multiple gate lines, reducing the total number of separate connections needed and minimizing the non-display area.
Data Source
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AI summary
A display panel includes: a display area including: a curved boundary in plan view, and a pixel array including pixel rows, and a non-display area in a periphery of the display area, and including: a curved boundary in plan view, a plurality of gate blocks arranged along the curved boundary of the non-display area, and at least one dummy block among the gate blocks, and a plurality of link lines configured to connect the gate blocks to the pixel rows, at least one of the link lines being multi-segmented to include a plurality of segments oriented in different directions in plan view.