Multi-Sense Amplifier Memory Access via Time-Division Multiplexing
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Solution Overview
Problem
Conventional multi-port memory architectures face challenges in achieving high-speed data transfer due to area and power consumption, with pseudo dual-port memory solutions resulting in narrower data paths and lower bandwidth, and true multi-port memories requiring complex arbitration and latency penalties.
Innovation Solution
The implementation of a pseudo dual-port I/O circuit with multiple sense amplifiers and multiplexors allows for simultaneous read and write operations in a single clock cycle by alternating the connection of sense amplifiers and data paths, enabling efficient consecutive read operations without significant delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If true multi-port memory architecture is used, then simultaneous read and write operations can be performed, but area and power consumption increase significantly
Solution Approach 1:
The memory array is divided into multiple banks, where each bank is a separate memory cell that can be independently accessed. This segmentation allows multiple read operations to be performed simultaneously on different banks within a single clock cycle, achieving multi-port functionality without requiring each memory cell to have multiple ports, thus reducing the area per memory cell while maintaining high data transfer speed
Solution Approach 2:
Single-port memory cells are designed to serve multiple functions by being accessible through different banks. Each memory cell can be part of different banks that are accessed simultaneously, allowing the same memory cell structure to participate in multiple read operations or read-write operations at the same time, thereby achieving multi-port functionality with single-port cells and reducing overall area and power consumption
2Area of stationary object
If pseudo dual-port memory with time-domain multiplexing is used, then area is reduced, but data path width and bandwidth are narrowed
Solution Approach 1:
The memory is segmented into multiple banks that can operate in parallel. Each bank has its own data path, allowing multiple data paths to exist simultaneously rather than time-multiplexing a single data path. This maintains full bandwidth for each data path while reducing area by using standard single-port memory cell structures, avoiding the bandwidth limitation of pseudo dual-port approaches
Solution Approach 2:
Instead of time-multiplexing operations on a single data path (temporal dimension), the invention uses spatial parallelism by creating multiple banks with multiple simultaneous data paths. This dimensional shift from time-based to space-based parallelism maintains full bandwidth while achieving the area efficiency of single-port cells
3Area of stationary object
If conventional single-port SRAM is used, then area and power are efficient, but only one operation can be performed per clock cycle
Solution Approach 1:
The memory array is divided into multiple independently accessible banks. Each bank can be accessed simultaneously through its own address decoder and data path, allowing multiple read operations or read-write operations to occur in parallel within a single clock cycle. This maintains the area and power efficiency of single-port memory cells while achieving multi-operation capability through bank-level parallelism
Solution Approach 2:
The memory system dynamically routes address signals to different banks based on the read address, allowing flexible and simultaneous access to multiple banks. The bank selection logic dynamically determines which banks to access based on the address bits, enabling multiple operations per clock cycle while maintaining efficient single-port cell structures
Data Source
AI summary
A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.