Multi-Sensor Image Processing System With Trigger-Based Segmentation
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Solution Overview
Problem
The existing System-on-Chip (SoC) technologies face latency issues during on-the-fly processing of images from multiple sensors with different resolutions, frame rates, and exposure values, leading to degraded image quality due to the need for stitching image lines.
Innovation Solution
A system comprising an access serializer, trigger controllers, FIFO memory, and an image signal processing (ISP) pipeline circuit that processes input image lines based on trigger IDs and configuration parameters, avoiding stitching and maintaining image quality across different sensor parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If image lines from multiple sensors are stitched together to generate a large image stream, then the system can process images from different sensors, but latency increases due to the stitching process
Solution Approach 1:
The patent divides the image processing into independent sensor channels, where each sensor's image lines are processed separately through dedicated pipelines rather than being merged and stitched together. This segmentation eliminates the stitching operation that causes latency, while still allowing multi-sensor processing through parallel independent channels.
Solution Approach 2:
The patent implements preliminary processing of each sensor's image lines individually before any merging or combination occurs. By preparing and processing images from different sensors in advance through separate pipelines, the system reduces the time needed for subsequent stitching operations and overall processing latency.
2Adaptability or versatility
If image lines are stitched together to create a unified image stream, then multiple sensors can be integrated, but image quality degrades due to different exposure values and resolutions
Solution Approach 1:
The patent applies different processing parameters and quality settings to each sensor's image lines according to their specific characteristics (resolution, exposure value, frame rate). Each sensor channel maintains its native quality parameters throughout processing, avoiding the quality degradation that occurs when forcing uniform processing across all sensors during stitching operations.
Solution Approach 2:
By segmenting the processing into separate sensor-specific pipelines, the patent allows each sensor's image data to be processed according to its native parameters without being compromised by the need to match other sensors' characteristics. This maintains individual image quality while still enabling multi-sensor integration through parallel processing.
3Adaptability or versatility
If different frame rates are handled by storing and stitching image lines, then images from sensors with varying frame rates can be processed, but processing efficiency decreases
Solution Approach 1:
The patent segments the processing into independent sensor channels, allowing each sensor to be processed at its own native frame rate without affecting other sensors. This eliminates the need for frame rate synchronization and stitching operations, significantly improving processing efficiency while maintaining the ability to handle diverse frame rates from multiple sensors.
Solution Approach 2:
The patent implements dynamic processing where each sensor channel operates independently at its own optimal frame rate, allowing the system to adapt to varying frame rates in real-time without forced synchronization. This dynamic approach processes images as they arrive from each sensor, maximizing throughput and efficiency.
Data Source
AI summary
A system for processing multiple images includes an access serializer, trigger controllers, a first-in-first-out (FIFO) memory, and an image signal processing (ISP) pipeline circuit. The access serializer serializes access requests that are associated with processing of input image lines of the images. The trigger controllers decode corresponding serialized access requests to generate trigger identifiers (IDs), respectively. The FIFO memory receives a corresponding trigger ID from each trigger controller and provides the trigger IDs to the ISP pipeline circuit based on an order of reception of the trigger IDs. The ISP pipeline circuit receives the input image lines associated with the trigger IDs, and based on a corresponding set of configuration parameters associated with the input image lines, processes the input image lines in an order of reception of the trigger IDs, to generate processed image lines, respectively.