Multi-Sequencer Thread Execution via User-Level Instructions

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Solution Overview

Problem

Current information processing systems face limitations in efficiently managing and scheduling user-level threads without operating system intervention, leading to suboptimal performance and resource utilization.

Innovation Solution

The implementation of a multi-sequencer system with user-level instructions, such as SXFR and SEMONITOR, allows for inter-sequencer control and proxy execution mechanisms, enabling thread creation, control, and synchronization without OS intervention, and masking asymmetry among sequencers to appear uniform to user-level programs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If user-level threads are scheduled without operating system intervention, then thread management efficiency is improved, but system complexity increases due to the need for additional mechanisms to manage thread creation, control, and synchronization

Engineering Contradiction:

Improvethread management efficiencyVSAvoidthread management mechanism complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a user-level thread library as an intermediary between user-level threads and the operating system. This thread library provides mechanisms for thread creation, control, and synchronization without requiring OS intervention, thereby improving thread management efficiency while managing complexity through a dedicated software layer that abstracts the underlying complexity from both the OS and user applications.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If multiple instruction sequencers are used to execute threads in parallel, then system performance is improved, but device complexity increases due to the need for inter-sequencer control and coordination mechanisms

Engineering Contradiction:

Improvesystem performanceVSAvoidinter-sequencer control complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces hardware-based inter-sequencer control mechanisms with software-based solutions. Instead of implementing complex hardware control logic for coordinating multiple instruction sequencers, the system uses user-level instructions and a thread library to manage thread execution across sequencers, substituting mechanical/hardware complexity with software flexibility.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If the operating system manages all processors, then system reliability is improved through centralized control, but the number of processors that can be efficiently managed is limited

Engineering Contradiction:

Improvecentralized control reliabilityVSAvoidprocessor management scalability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments processor management into two layers: OS-managed processors for system-critical tasks and user-level threads for application-specific parallelism. This segmentation allows the OS to maintain reliable centralized control over a manageable subset of processors while user-level threads can utilize additional processors independently, thereby scaling the system beyond OS limitations without compromising reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent adds a new dimension to processor management by introducing user-level thread execution as a separate layer above OS management. Instead of solely relying on vertical OS control, the system enables horizontal user-level parallelism that operates independently of OS processor limits, effectively expanding the manageable processor count through a dimensional addition to the management architecture.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8719819B2Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Publication Date: 2014.05.06 INTEL CORP

AI summary

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.