Multi-Shared Pixel Architecture Dual Readout Path

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Solution Overview

Problem

As pixel counts increase in digital electronic devices, the shrinking pixel size negatively affects readout speed, and conventional high-speed designs are complex and costly, necessitating a novel image sensor solution.

Innovation Solution

A multi-shared pixel architecture with a dual readout path is implemented, utilizing a switch unit between floating diffusion nodes of M-shared and N-shared pixel architectures to enhance readout speed and throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If pixel counts increase and pixel sizes shrink, then the image sensor can capture more visual information, but the readout speed decreases

Engineering Contradiction:

Improvepixel countVSAvoidreadout speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The image sensor is divided into multiple pixel groups, where each group shares common readout circuitry. This segmentation allows parallel processing of signals from different pixel groups, effectively increasing the overall readout speed despite having a high total pixel count.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple pixel groups are merged to share common floating diffusion nodes and readout circuits. By combining the readout paths of multiple pixels through shared nodes, the patent reduces the total number of independent readout circuits needed, thereby maintaining high readout speed while supporting increased pixel counts.

Inventive Principle:

Principle #5Merging (Combining)

2Speed

If conventional high speed circuit design is used, then the frame rate improves, but the device complexity and chip area increase

Engineering Contradiction:

Improveframe rateVSAvoidcircuit complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The floating diffusion nodes and readout circuits are designed to serve multiple pixel groups simultaneously. This multi-functional design allows the same hardware components to handle readout operations for different pixel groups, reducing overall circuit complexity while maintaining high frame rates.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Shared floating diffusion nodes act as intermediaries between multiple pixel groups and the final readout circuits. These intermediary nodes buffer and consolidate signals from multiple pixels before they reach the readout amplifiers, simplifying the overall circuit architecture while enabling high-speed operation.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If conventional high speed circuit design is used, then the frame rate improves, but the chip area and cost increase

Engineering Contradiction:

Improveframe rateVSAvoidchip area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

Multiple pixel readout paths are merged to share common floating diffusion nodes and readout circuits. This consolidation reduces the total chip area required for readout functionality while maintaining high frame rates, as fewer independent circuits are needed compared to a fully parallel architecture.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The readout circuits and floating diffusion nodes are designed with multi-functionality to serve multiple pixel groups. This universal design reduces the overall chip area by eliminating redundant circuitry, as the same components perform readout functions for different pixel groups at different times.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9467637B2Image sensor with multi-shared pixel architecture and dual readout path

Publication Date: 2016.10.11 HIMAX IMAGING LIMITED

AI summary

An image sensor includes an M-shared pixel architecture, an N-shared pixel architecture and a switch unit, wherein M is an integer not smaller than two and N is an integer not smaller than two. The switch unit is coupled between a floating diffusion node of the M-shared pixel architecture and a floating diffusion node of the N-shared pixel architecture.