Multi-Silicide Transistor Gate Structure for Lower Gate Resistance
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Solution Overview
Problem
Conventional CMOS transistor structures use the same silicide material on the source, drain, and gate, which can lead to increased resistance and inefficiencies in semiconductor device performance.
Innovation Solution
A structure for a transistor is designed with a first dielectric spacer, a second dielectric spacer, and a gate with a first silicide layer extending between them, along with a second silicide layer within the first and contacts aligned to these layers, allowing for separate formation of silicide layers on the gate and source/drain regions, reducing gate resistance without affecting the source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same silicide material is formed on the source, drain, and gate, then the manufacturing process is simple, but the gate resistance increases and device performance deteriorates
Solution Approach 1:
The patent divides the silicide formation process into separate stages: first forming a gate silicide layer on the gate electrode, then forming a source/drain silicide layer on the source and drain regions. This segmentation allows each region to have optimized silicide properties, reducing gate resistance while maintaining manufacturing feasibility through sequential processing steps.
Solution Approach 2:
The patent applies different silicide materials or configurations to different regions: the gate receives a specific silicide layer optimized for low resistance, while source/drain regions receive silicide optimized for their specific requirements. This local differentiation resolves the contradiction by allowing region-specific optimization without requiring a completely uniform process.
2Reliability
If separate silicide layers are formed on the gate and source/drain regions, then gate resistance is reduced and device performance is enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent forms the gate silicide layer in advance during the gate fabrication stage, before source/drain processing. This preliminary action allows the gate silicide to be optimized independently, and subsequent source/drain silicide formation can proceed without interfering with the already-optimized gate structure, managing complexity through staged processing.
Solution Approach 2:
The patent introduces dielectric spacers as intermediary elements that define the boundaries between gate and source/drain regions during the separate silicide formation process. These spacers act as masks and structural guides, enabling the complex separate silicide formation to proceed in a controlled, systematic manner that manages process complexity.
3Reliability
If a silicide layer is formed on the gate, then gate resistance is reduced, but the integrity of the source/drain regions may be compromised
Solution Approach 1:
By segmenting the silicide formation into separate gate and source/drain steps, the patent prevents the silicide formation process from simultaneously affecting all regions. The gate silicide is formed first under controlled conditions, and subsequent source/drain silicide formation is spatially separated, preventing contamination or damage to source/drain region integrity.
Solution Approach 2:
Dielectric spacers serve as intermediary protective layers that physically separate the gate from source/drain regions during silicide formation. These spacers prevent unwanted interactions between the gate silicide process and source/drain regions, maintaining source/drain integrity while allowing gate silicide formation to proceed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces gate resistance and maintains the integrity of the source/drain regions by decoupling the formation of silicide layers, enhancing semiconductor device performance.
Implementation Method 1
The silicide may be formed by a thermally-stimulated reaction between a metal or a metallic alloy thin film and the contacted semiconductor material
Data Source
AI summary
Structures for a transistor and methods of forming a structure for a transistor. The structure includes a first dielectric spacer, a second dielectric spacer, and a gate laterally between the first dielectric spacer and the second dielectric spacer. The gate includes a first silicide layer extending from the first dielectric spacer to the second dielectric spacer. The structure further includes a second silicide layer within the first silicide layer, and a contact that is aligned to the second silicide layer.