Multi-Site Testing Holder With Pressure-Releasing Device

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Solution Overview

Problem

There is a lack of low-cost solutions for verifying incoming chips as known good dies in the manufacturing of three-dimensional integrated circuits, particularly for chip on chip on substrate (CoCoS) and chip on wafer on substrate (CoWoS) configurations before packaging, and existing methods are often manual and inefficient.

Innovation Solution

A testing flow and holder design that allows for simultaneous testing of multiple chip units, including a multi-site holding frame with pressure-releasing features to prevent damage during insertion and a method for verifying diced chips or die packages, reducing system-level failures and manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual testing methods are used for verifying incoming chips as known good dies, then testing can be performed, but testing efficiency is low and production time is excessive

Engineering Contradiction:

Improvetesting efficiencyVSAvoidproduction time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The testing system is segmented into multiple independent testing sites (e.g., 4-site, 9-site, 16-site configurations), where each site can test a chip unit independently. This allows parallel processing of multiple chips simultaneously, dramatically increasing testing throughput and reducing overall production time while maintaining comprehensive verification of each chip unit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple testing functions are merged into a single integrated holder system that can accommodate and test multiple chip units simultaneously. The holder combines multiple testing sites, pressure releasing devices, and support structures into one unified apparatus, enabling efficient batch testing while reducing the need for multiple separate testing stations.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If chip units are inserted into testing holders without pressure releasing features, then testing can be performed, but insertion damage may occur to the chip units

Engineering Contradiction:

Improvechip unit integrityVSAvoidinsertion damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The holder incorporates pressure releasing devices positioned at strategic locations where excessive insertion force may be applied. These devices act as mechanical cushions or compliance features that absorb insertion shock and prevent damage to the chip unit during the loading process, ensuring chip integrity before testing begins.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The pressure releasing device serves as an intermediary element between the insertion mechanism and the chip unit. It mediates the force transfer during insertion, allowing controlled deformation or force dissipation that protects the fragile chip unit from direct impact while still enabling proper seating and electrical contact.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If multiple chip units are tested simultaneously using a multi-site holder, then testing throughput increases, but holder design complexity increases

Engineering Contradiction:

Improvetesting throughputVSAvoidholder design complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The multi-site holder is designed with universal features that allow it to test multiple chip units with potentially different configurations. The holder incorporates standardized testing interfaces, reusable pressure releasing devices, and modular site configurations that can accommodate various chip types, reducing the need for multiple specialized holders and simplifying overall system design.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The holder employs a nested or modular structure where multiple testing sites are arranged in a compact, space-efficient configuration. Sites may be nested within a common frame structure, sharing common support elements, electrical connections, and control mechanisms, thereby reducing overall complexity while maintaining high testing throughput.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS11579190B2Testing holders for chip unit and die package

Publication Date: 2023.02.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.