Multi-Size Solder Bumps on UBM Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flip chip interconnection technologies face challenges in reducing residual stress in under-bump metallization (UBM) layers and efficiently forming multi-size solder bumps with significant height differences on a single substrate, leading to defects like peeling and cracking, and increased production costs due to separate formation of bigger and smaller bumps.
Innovation Solution
A substrate with a redistribution layer and insulation layers having openings, where UBM layers of titanium, chromium-copper alloy, and copper are deposited to form UBM pads of different sizes, followed by solder paste printing and reflowing to create both bigger and smaller solder bumps with over 100 μm height difference on a single substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional UBM metal stacks (Ti/NiV/Cu or Cr/CrCu/Cu) are used, then adhesion and wetting properties are improved, but residual stress causes peeling and cracking defects
Solution Approach 1:
The patent uses a composite UBM structure with multiple metal layers (Ti, Cr, Cu, Au) where each layer serves a specific function: Ti provides adhesion to the substrate, Cr provides oxidation resistance, Cu provides electrical conductivity and solder wetting, and Au provides final surface finish. This composite approach balances adhesion, wetting, and stress properties better than conventional single-stack approaches.
Solution Approach 2:
The patent modifies the UBM stack composition by replacing NiV with Cr and adjusting layer thicknesses. The Cr layer thickness is controlled at 50-200 nm to provide sufficient oxidation resistance while managing stress. The Cu layer thickness is optimized at 1-5 μm to balance conductivity and stress. These parameter changes reduce residual stress while maintaining adhesion and wetting properties.
2Manufacturing precision
If separate formation processes are used for bigger and smaller solder bumps, then manufacturing precision is improved, but productivity decreases and costs increase
Solution Approach 1:
The patent combines the formation of different-sized solder bumps into a single integrated process. The UBM pads are formed with different sizes in one patterning step, and solder bumps of different sizes are formed simultaneously in one soldering process. This merging eliminates the need for separate formation processes while maintaining size precision through the insulating layer opening design.
Solution Approach 2:
The patent applies local quality by creating UBM pads with different sizes at different locations on the substrate. The insulating layer has openings of different dimensions, which define the size of UBM pads and subsequently the solder bumps at each location. This allows each region to have the specific bump size required while being formed in a single process.
3Reliability
If UBM metals are deposited on insulation layers, then electrical connection is improved, but residual stress causes metal and polymer to peel and crack
Solution Approach 1:
The patent uses a composite UBM structure where Cr and Cu layers are deposited on the insulating layer. The Cr layer provides oxidation resistance and intermediate adhesion, while the Cu layer provides electrical conductivity and solder wetting. This composite structure distributes stress more effectively than a single metal layer, reducing peeling and cracking while maintaining electrical connection.
Solution Approach 2:
The patent controls the thickness parameters of the UBM layers to manage stress. The Cr layer is kept thin (50-200 nm) to minimize stress accumulation at the metal-polymer interface, while the Cu layer is optimized at 1-5 μm to provide sufficient conductivity without excessive stress. These parameter controls maintain bond strength while ensuring electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces residual stress in UBM layers, enables the simultaneous formation of multi-size solder bumps with considerable height differences on a single substrate, improving process throughput and reducing costs by eliminating the need for separate bump formation and additional process steps.
Implementation Method 1
A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer.
Implementation Method 2
The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads.
Data Source
AI summary
An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.