Multi-SoC Data Processing via External Circuit Segmentation
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Solution Overview
Problem
The existing multi-core and multi-cluster technologies, such as GIC, CMN, and CCIX, do not effectively address the need for cooperation among multiple System on a Chip (SoCs) to achieve high arithmetic capability, leading to higher research, development, and manufacturing costs for electronic products, as they do not leverage the potential of combining multiple SoCs with low arithmetic capabilities to enhance processing performance.
Innovation Solution
A data processing device comprising multiple SoCs, where one SoC processes part of the input data and transmits it to another via an external circuit, allowing both SoCs to work together to achieve higher processing performance than either could alone, by dividing input data into parts and processing them in a performance-enhancing mode, with each SoC handling specific portions of the data to generate output that can be combined seamlessly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple SoCs with different arithmetic capabilities are used to achieve high processing performance, then the processing capability is improved, but the research, development, and manufacturing cost increases
Solution Approach 1:
The patent divides the data processing task into multiple segments, with each SoC handling a specific portion of the input data. The first SoC processes a first input part to generate first output data, while the second SoC processes a second input part to generate second output data. This segmentation allows multiple low-end SoCs to collectively achieve the processing capability of a high-end SoC, reducing R&D and manufacturing costs while maintaining high productivity through parallel processing of divided data segments
2Productivity
If a single SoC with high arithmetic capability is used, then the processing performance is high, but the cost-effectiveness decreases
Solution Approach 1:
The patent merges the processing capabilities of multiple low-end SoCs to achieve the performance of a single high-end SoC. By combining the first SoC and second SoC, each with low arithmetic capability, the system achieves high processing performance through coordinated operation. The merging of multiple identical or similar SoCs improves cost-effectiveness while maintaining high productivity, as these SoCs can be mass-produced at lower costs compared to single high-performance SoCs
3Ease of manufacture
If multiple same/similar SoCs with low arithmetic capabilities are combined, then the cost is reduced, but the processing performance may be insufficient without proper cooperation mechanisms
Solution Approach 1:
The patent introduces a transceiver circuit as an intermediary component that enables effective cooperation between multiple SoCs. The transceiver circuit facilitates data transmission between the first SoC and second SoC, allowing them to work together as a unified processing system. This intermediary mechanism ensures that multiple low-cost SoCs can achieve high processing performance through coordinated operation, resolving the contradiction between cost reduction and performance maintenance
Data Source
AI summary
Disclosed is a data processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first central processing unit (CPU) dividing to-be-processed data into a first input part and a second input part, and processing the first input part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit, and transmitting the second output data to the main SoC via the external circuit; and a second CPU receiving the second input part from the second transceiver circuit and processing it to provide the second output data for the second transceiver circuit.