Multi-SoC Time Synchronization Using Offset Averaging
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Solution Overview
Problem
Existing electronic devices with multiple systems on a chip face challenges in synchronizing these systems effectively, particularly when transmission delays between the systems are not constant, which affects the alignment of time bases and overall device performance.
Innovation Solution
A modified Precision Time Protocol (PTP) technique is used to synchronize primary and secondary systems on a chip by periodically sending time synchronization messages through an inter-SoC interface, allowing the secondary SoC to calculate a time offset and align its time base with the master clock, while accounting for variable transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional PTP synchronization is used between multiple systems on a chip, then time base alignment can be achieved, but synchronization precision deteriorates when transmission delays are not constant
Solution Approach 1:
The patent measures and stores transmission delay characteristics in advance during a calibration phase, then uses these pre-measured delay values to compensate for timing errors during actual synchronization operations. This preliminary measurement action allows the system to account for variable delays without compromising real-time synchronization precision.
Solution Approach 2:
The patent implements a feedback mechanism where the secondary SoC sends timestamped messages back to the primary SoC, allowing the primary SoC to measure round-trip transmission delays and adjust synchronization accordingly. This closed-loop feedback enables continuous compensation for variable transmission delays, maintaining synchronization reliability.
2Device complexity
If multiple systems on a chip operate independently, then device complexity is reduced, but coordination between systems deteriorates
Solution Approach 1:
The patent introduces an intermediary synchronization protocol that mediates between independent SoCs. The primary SoC acts as a time master that distributes synchronized timestamps to secondary SoCs through an inter-SoC interface, allowing independent operation while maintaining coordination through this intermediary synchronization mechanism.
3Measurement precision
If transmission delay compensation is implemented, then synchronization precision is improved, but device complexity increases
Solution Approach 1:
The patent uses timestamp copying and replication across multiple SoCs. Each SoC maintains a copy of the synchronized time base by receiving and storing timestamps from the primary SoC, eliminating the need for complex real-time delay calculation mechanisms while maintaining precision through simple timestamp replication and offset application.
Data Source
AI summary
An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases and an inter-SoC interface that connects the first and second SoCs. The operations of the first and second SoCs are synchronized by aligning the time bases for the SoCs using a modified PTP technique. The technique includes the second SoC receiving a time synchronization message from the first SoC over the inter-SoC interface, recording a local timestamp of receipt of the time synchronization message, receiving a master timestamp corresponding to a timestamp recorded by the first SoC corresponding to the time of sending the time synchronization message by the first SoC, and calculating a time offset between the local timestamp and the master timestamp. The time bases of the first SoC and second SoC are then aligned using the calculated time offset. To account for transmission delays, multiple time offsets may be averaged.