Multi-Solder Die Interconnect Assembly for High-Density Packaging
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Solution Overview
Problem
Conventional IC packages are limited in interconnect density due to solder interconnects, requiring costly manufacturing operations and specialized equipment, leading to reduced yields and increased complexity.
Innovation Solution
The use of multi-layer die subassemblies with different solder materials for interconnects, including no remelt solder and higher-temperature solder, along with a redistribution layer (RDL) design with inverted vias, to achieve high interconnect density without excessive manufacturing costs or complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional solder interconnects are used to couple dies together, then manufacturing simplicity is maintained, but interconnect density is limited
Solution Approach 1:
The patent divides the interconnect structure into multiple layers with different solder materials. First solder interconnects with a first solder material are formed at a first level, and second solder interconnects with a second solder material are formed at a second level. This segmentation allows each layer to use optimized solder materials for different density requirements, achieving high overall interconnect density while maintaining manufacturing feasibility through modular construction
Solution Approach 2:
Different solder materials are assigned to different spatial locations and levels within the interconnect structure. The first solder material is used for first-level interconnects while the second solder material is used for second-level interconnects. This local differentiation allows optimization of solder properties (such as melting point, wetting characteristics, and mechanical strength) for specific interconnect requirements at each level, enabling high density without uniform complexity throughout the entire structure
2Quantity of substance
If higher interconnect density is achieved through conventional methods, then manufacturing costs increase, but yields remain reduced
Solution Approach 1:
By segmenting the interconnect formation into multiple levels with different solder materials, the patent enables parallel processing and modular assembly. This segmentation allows manufacturing processes to be optimized independently for each level, improving overall yield by reducing the cumulative effect of defects and enabling better quality control at each stage while achieving high interconnect density
3Quantity of substance
If multi-layer die subassemblies with different solder materials are used, then interconnect density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by assigning different solder materials to specific levels and locations within the interconnect structure. The first solder material is used for first-level interconnects and the second solder material for second-level interconnects. This localized material differentiation allows each level to be manufactured with precision optimized for its specific requirements, rather than requiring uniform high precision across all levels, thereby achieving high interconnect density while managing manufacturing precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves higher interconnect densities with reduced risk of die shifting and lower total thickness variation, improving yields and reducing manufacturing complexity while maintaining flexibility in design.
Implementation Method 1
first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.