Multi-Spacer Hosting Structure for Nanometric Device Integration
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Solution Overview
Problem
Current microelectronics technologies face limitations in reducing device dimensions below 100 nm due to physical constraints and the high costs and complexity of advanced lithography techniques, while existing solutions are mainly focused on Flash memory devices and require micrometric base components.
Innovation Solution
A hosting structure and manufacturing method for nanometric electronic devices, featuring multiple spacers levels with conductive and insulating materials to create nanometric hosting seats with conduction terminals, allowing for the orientation and integration of nanometric molecular components with varying ends and dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography processes are used to reduce device dimensions, then manufacturing precision improves, but device complexity and cost increase significantly below 100 nm
Solution Approach 1:
The patent segments the device structure into multiple hierarchical levels (first level with first spacers, second level with second spacers, third level with third spacers). Each level is formed through separate controlled deposition and selective removal cycles, allowing nanometric precision to be achieved through iterative refinement rather than single-step lithography.
Solution Approach 2:
The patent transitions from planar 2D patterning to 3D multi-level structures. By forming spacers at different vertical levels (first multi-spacer level, second multi-spacer level, third multi-spacer level) with varying orientations (parallel, transversal, alternating), the invention achieves nanometric dimensional control through vertical stacking rather than horizontal scaling alone.
2Manufacturing precision
If advanced lithography techniques (x-ray, extreme UV, electronic beam) are used to achieve sub-100 nm dimensions, then manufacturing precision improves, but productivity decreases due to excessively long etching times
Solution Approach 1:
The patent employs self-aligned spacer formation where each spacer level automatically positions itself relative to previous levels. The controlled deposition of materials followed by selective removal creates spacers that are inherently aligned without requiring additional lithographic alignment steps, eliminating the need for complex alignment procedures and reducing overall process time.
Solution Approach 2:
The patent performs preliminary structured deposition of multiple material layers (conductive and insulating) before final spacer formation. By pre-organizing materials in alternating patterns at each level, the selective removal process automatically generates precisely positioned spacers, eliminating the need for time-consuming post-deposition alignment and patterning steps.
3Manufacturing precision
If existing nanometric structures are designed for Flash memory devices, then manufacturing precision for specific applications improves, but adaptability decreases for other device types
Solution Approach 1:
The patent creates a universal hosting structure with multiple conductive spacers and insulating spacers arranged in alternating patterns across three levels. This multi-level alternating spacer configuration can accommodate various device architectures (transistors, diodes, memory elements) by selectively connecting different spacer combinations, making the same nanometric structure adaptable to multiple device types without requiring redesign.
Solution Approach 2:
The patent enables local customization of device properties by selectively removing or connecting specific spacers at different levels. Each hosting seat can be locally configured with different conductor-insulator patterns, allowing different device functions (n-type, p-type, memory, logic) to be realized in different regions of the same nanometric structure through localized material removal or connection establishment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the realization of nanometric electronic devices with high integration density and versatility in hosting components with multiple terminals, overcoming dimensional limitations and facilitating the integration of molecular transistors and other nanometric components.
Implementation Method 1
depositing, above a substrate, of a block seed having at least one side wall substantially perpendicular to said substrate; repeating n times, with n≧2, of a step comprising a deposition, on said block seed and on said substrate, of alternating materials
Implementation Method 2
an anisotropic etching of said deposited layer, with realization, at each repetition, of at least a relative spacer substantially perpendicular to said substrate
Data Source
AI summary
A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.