Multi-Stack Chip Package Wire Bonding Reliability
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Solution Overview
Problem
In stack-type semiconductor devices, particularly NAND-type flash memory, the long bonding wires connecting top-layer semiconductor chip electrodes to lead frames are prone to short-circuiting and deformation during the wire bonding process, leading to reliability issues and increased manufacturing complexity.
Innovation Solution
A stack-type semiconductor device structure where semiconductor chips with electrode pads of the same electric potential are connected via stud bumps and bonding wires, reducing the number of bonding steps and wire length, and sealed with resin to prevent short-circuits, while using a lead frame with inner leads of varying lengths to facilitate efficient chip mounting and bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to connect top layer semiconductor chip electrodes to lead frame, then electrical connection is achieved, but wire deformation and short-circuit occur during wire bonding process
Solution Approach 1:
The patent introduces an intermediary structure (lower semiconductor chip with electrode pads) between the top layer chip and lead frame. This intermediary serves as a bonding platform, allowing bonding wires to connect to the intermediate chip rather than spanning the entire distance to the lead frame, thereby reducing wire length and preventing deformation and short-circuit issues.
Solution Approach 2:
The patent segments the bonding path into multiple stages: first bonding wires connect top layer chip electrodes to the intermediary chip, then separate bonding wires connect the intermediary chip to the lead frame. This segmentation breaks down the single long bonding operation into shorter, more reliable connections.
2Reliability
If multiple bonding steps are used to connect electrode pads via lower semiconductor chip, then electrical connection is achieved, but manufacturing complexity and time increase
Solution Approach 1:
The patent merges multiple bonding operations into a single wire bonding process. By forming stud bumps on the lower chip before mounting upper chips, the bonding wires can simultaneously establish multiple electrical connections in one operation, rather than requiring separate bonding steps for each connection.
Solution Approach 2:
The patent performs preliminary actions by forming stud bumps on the lower semiconductor chip electrode pads before mounting the upper semiconductor chips. This preliminary preparation enables the wire bonding process to proceed more efficiently, as the bonding targets are already prepared and positioned correctly.
3Reliability
If long bonding wires are used to connect top layer chip to lead frame, then electrical connection is achieved, but wire short-circuit risk increases during resin sealing
Solution Approach 1:
The lower semiconductor chip acts as an intermediary bonding platform, allowing bonding wires to make intermediate connections rather than spanning the full distance. This reduces wire length and the associated risk of short-circuit during resin sealing, as shorter wires are less prone to deformation and contact with adjacent wires.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of the stack-type semiconductor device by reducing wire deformation and short-circuit risks, simplifying the manufacturing process, and allowing for downsized chip design with improved wiring efficiency.
Implementation Method 1
a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole
Implementation Method 2
a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires
Data Source
AI summary
A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.