Multi-Stack Packaging Chip Cavity Design
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Solution Overview
Problem
Conventional wire bonding methods for packaging circuit elements increase parasitic capacitance, chip size, and prevent stack structure formation due to the need for bonding pads and wires, which deteriorate chip performance and limit the ability to form additional wafers on cap wafers.
Innovation Solution
A multi-stack packaging chip is developed using flip-chip packaged chips with circuit elements on cap wafers, where a second cap wafer with a cavity is combined to position a third circuit element, and solder is used to electrically couple the second cap wafer to a packaging substrate, along with insulating layers to isolate the third circuit element from the substrate, allowing for a compact stack structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect circuit element to external power source, then electrical connection is achieved, but parasitic capacitance increases and chip performance deteriorates
Solution Approach 1:
The patent removes the wire bonding structure entirely by using a flip-chip configuration where the circuit element is directly connected to the packaging substrate through bonding pads on the substrate, eliminating the source of parasitic capacitance while maintaining electrical connectivity
Solution Approach 2:
The patent transitions from a planar wire bonding approach to a three-dimensional flip-chip architecture, where the circuit element is mounted face-down on the substrate, allowing direct vertical electrical connection through bonding pads and eliminating the need for lateral wire connections
2Reliability
If bonding pad is formed around circuit element for wire bonding, then electrical connection is achieved, but chip size increases
Solution Approach 1:
The patent eliminates the need for additional bonding pads on the circuit element by using the substrate's bonding pads directly for electrical connection, removing the extra area requirement while maintaining connectivity
Solution Approach 2:
The flip-chip configuration allows bonding pads to be positioned on the substrate rather than requiring peripheral pads on the circuit element, enabling more efficient space utilization and reducing overall chip footprint
3Reliability
If wire bonding structure is used, then electrical connection is achieved, but stack structure formation is prevented
Solution Approach 1:
By removing the wire bonding structure entirely, the patent enables the cap wafer surface to be used for mounting additional circuit elements, making stack structure formation possible
Solution Approach 2:
The flip-chip architecture transitions from a single-layer planar structure to a multi-layer vertical stack, where cap wafers can be sequentially mounted on top of each other, enabling three-dimensional integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, minimizes chip size, and enables the formation of stack structures by eliminating the need for bonding pads and wires, enhancing chip performance and allowing for the integration of multiple circuit elements in a compact, multifunctional design.
Implementation Method 1
a solder formed on the second cap wafer at a distance from the third circuit element and electrically coupling the second cap wafer to a packaging substrate
Data Source
AI summary
A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.