Multi-Stack Memory Device Common Wire Integration
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Solution Overview
Problem
Conventional multi-stack memory devices face challenges in increasing recording density per unit area due to structural complexity, making it difficult to maintain a pitch of storage nodes or wirings below 4F, which deteriorates data retention characteristics and limits integration density.
Innovation Solution
A multi-stack memory device design where storage units are vertically stacked with a common wire connecting transistors across multiple rows, allowing for a pitch of 2F or less between storage nodes or wirings, thereby increasing recording density without reducing the line width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional connection methods are used with conductive plugs between every storage node or wiring, then the storage nodes can be connected to transistors, but the pitch increases to about 4F which reduces integration density
Solution Approach 1:
Multiple transistors connected to storage units in different rows share a common wire (gate line or bit line) instead of requiring separate connections. This merging of connection paths eliminates redundant conductive plugs and reduces the pitch from 4F to 2F or less, thereby increasing integration density while managing structural complexity
Solution Approach 2:
A single common wire serves multiple transistors across different storage unit rows, making the wire multi-functional. This universal connection approach allows one wire to connect to multiple transistors that access different storage units, reducing the total number of wires and plugs needed in the structure
2Quantity of substance
If the pitch of storage nodes or wirings is reduced below 4F, then integration density increases, but structural complexity makes connection maintenance difficult
Solution Approach 1:
The memory structure is divided into multiple storage unit rows grouped into storage node groups (e.g., first and second storage node groups with vertically stacked storage nodes). This segmentation allows systematic organization of connections, making it easier to maintain and manufacture even with reduced pitch by handling connections in organized groups rather than individual elements
Data Source
AI summary
Provided is a multi-stack memory device that includes a storage unit group including a plurality of storage units that are vertically stacked and form a plurality of storage unit rows, and a plurality of transistors connected to the storage unit group, wherein the transistors that are connected to the storage units which are included in at least two rows of the plurality of the storage unit rows and are connected by a common wire. The common wire may be a gate line or a bit line.