Multi-Stack Package-on-Package Structure Warpage Reduction
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Solution Overview
Problem
Conventional Integrated Fan-Out (InFO) processes face challenges in reducing warpage and footprint size of multi-stack packages due to the need for extensive solder regions and complex routing, which affects integration and yield rates.
Innovation Solution
The method involves forming a multi-stack package by stacking smaller semiconductor devices encapsulated in an encapsulating material without solder regions between them, allowing for vertical stacking and singulation at intermediate processing stages, which reduces warpage and footprint size, and includes testing known good packages to increase yield rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional InFO process with solder joints is used to bond top package to bottom package, then reliable electrical connection is achieved, but warpage and footprint size increase
Solution Approach 1:
The patent removes the solder joint layer from between stacked semiconductor devices, extracting the problematic intermediate connection layer that causes warpage and increases footprint. Devices are bonded directly to each other through their respective bonding pads, eliminating the need for solder balls or solder bumps that occupy additional space and create thermal expansion mismatches.
Solution Approach 2:
The patent transitions from a planar bonding approach to a vertical stacking approach, where multiple semiconductor devices are stacked in the thickness direction (Z-axis) rather than being arranged in a two-dimensional plane. This vertical integration reduces the footprint area while maintaining electrical connectivity through direct bonding interfaces between stacked devices.
2Reliability
If extensive solder regions are used to connect multiple die layers, then electrical connectivity is ensured, but warpage increases
Solution Approach 1:
The patent extracts and eliminates the solder region from the package structure, removing the source of thermal expansion mismatch and warpage. By bonding devices directly to each other without intermediate solder layers, the patent prevents the warpage that would otherwise be caused by differential thermal expansion between solder and semiconductor materials during temperature cycling.
Solution Approach 2:
The patent employs bonding pads with composite material structures that provide both electrical conductivity and mechanical bonding strength without requiring solder. The bonding pads may include multiple material layers designed to match thermal expansion coefficients and provide reliable direct bonding interfaces between stacked devices.
3Reliability
If complex routing is implemented to connect through-molding vias and device die, then electrical connections are established, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the electrical connection paths into localized bonding pad regions on each device, eliminating the need for complex through-molding vias and redistribution layers. Each device maintains its own bonding pads that directly connect to corresponding pads on adjacent devices, simplifying the routing architecture from a complex multi-layer via system to a simple direct-bond interface.
Solution Approach 2:
Instead of routing signals through complex internal via structures from the bottom up, the patent inverts the approach by establishing direct bonding pad-to-bonding pad connections at each interface between stacked devices. This eliminates the need for through-molding vias that extend through the entire package thickness and require complex routing planning.
4Productivity
If multi-stack packages are formed with intermediate solder layers, then device integration is achieved, but yield rate decreases due to manufacturing complexity
Solution Approach 1:
The patent extracts and eliminates the intermediate solder layers from the multi-stack package structure, removing a critical failure point in the manufacturing process. By bonding devices directly to each other without solder, the patent eliminates solder-related defects such as voids, cracks, and poor wetting that would otherwise reduce yield rates during assembly and testing.
Solution Approach 2:
The patent performs bonding pad preparation and alignment verification before stacking devices, ensuring that bonding interfaces are properly prepared in advance. This preliminary action includes forming bonding pads with appropriate materials and geometries, and verifying alignment between stacked devices, which prevents bonding failures and improves yield rates during the actual stacking process.
Data Source
AI summary
Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.