Multi-Stage CDR Circuit for High-Frequency Jitter Reduction
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Solution Overview
Problem
Existing receiving circuits in test devices struggle with high-frequency jitter, leading to data transmission errors and poor signal quality, especially in environments with severe jitter.
Innovation Solution
A receiving circuit with multiple stages of clock data recovery (CDR) circuits, where each stage samples and recovers the clock signal, effectively reducing high-frequency jitter in a stepwise manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-stage clock data recovery circuit is used, then the device complexity is low, but the high-frequency jitter reduction capability is insufficient
Solution Approach 1:
The patent divides the clock data recovery process into multiple stages (first CDR circuit, second CDR circuit, third CDR circuit), where each stage handles specific frequency components of jitter. The first stage recovers clock from serial data, the second stage further cleans the signal, and the third stage provides final refinement, systematically segmenting the complex task of high-frequency jitter reduction across multiple manageable circuits
2Manufacturing precision
If multiple stages of CDR circuits are connected in cascade, then the high-frequency jitter is significantly reduced, but the device complexity increases
Solution Approach 1:
The receiving circuit is segmented into three distinct CDR stages, each optimizing for specific signal quality aspects. The first stage establishes basic clock recovery, the second stage refines signal cleanliness, and the third stage achieves final precision, with each segment contributing to overall manufacturing precision while managing complexity through functional division
Solution Approach 2:
Each CDR stage performs preliminary cleaning of the signal before it enters the next stage. The first stage preliminarily recovers the clock signal, the second stage preliminarily removes high-frequency jitter components, and the third stage performs final preliminary refinement, systematically preparing the signal for optimal quality through sequential preliminary actions
Data Source
AI summary
A receiving circuit of a test device includes a first data sampling circuit that samples a data signal using a first recovery clock, a second data sampling circuit that samples an output signal of the first data sampling circuit using a second recovery clock, and a third data sampling circuit that samples an output signal of the second data sampling circuit using a third recovery clock. The receiving circuit further includes a first clock recovery circuit that receives the data signal and generates the first recovery clock, a second clock recovery circuit that receives the output signal of the first data sampling circuit and generates the second recovery clock, and a third clock recovery circuit that receives the output signal of the second data sampling circuit and generates the third recovery clock.