Multi-stage Column ADC for CMOS Image Sensor Conversion
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Solution Overview
Problem
Current CMOS image sensors face limitations in achieving high-precision and high-speed analog-to-digital conversion due to the increased time required for bit determination in high-precision low-speed conversion, which restricts the number of determination times for low-precision high-speed conversion, making it challenging to satisfy both precision and speed requirements.
Innovation Solution
A solid-state image pickup device with a column ADC that performs AD conversion in multiple stages, including coarse, middle, and fine conversion, where each stage determines specific bits of the digital value by comparing the voltage at a retention node with a reference voltage, with progressively smaller voltage steps, allowing for higher-precision and higher-speed conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-precision low-speed AD conversion is used, then measurement precision is improved, but conversion speed deteriorates
Solution Approach 1:
The patent divides the AD conversion process into multiple conversion stages (first conversion stage, second conversion stage, third conversion stage, etc.), where each stage determines specific bits of the digital value. This segmentation allows the system to achieve high precision without requiring a single slow high-precision conversion, thereby improving overall conversion speed while maintaining measurement precision.
2Measurement precision
If resolution increases by one bit, then measurement precision is improved, but the number of determination times doubles
Solution Approach 1:
The patent segments the bit determination process across multiple conversion stages, where each stage handles specific bits (e.g., first stage determines most significant bit, second stage determines next bits, etc.). This segmentation prevents the exponential increase in determination times that would occur with a single-stage approach, allowing resolution to increase without proportionally increasing total conversion time.
Solution Approach 2:
The patent performs preliminary actions in earlier conversion stages by determining more significant bits first, which establishes a foundation for subsequent stages. This preliminary determination of upper bits allows later stages to focus only on refining the less significant bits, reducing the overall determination time compared to determining all bits sequentially in a single stage.
3Measurement precision
If column ADCs are provided for each vertical read line, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal multi-stage conversion architecture that can be applied across multiple column ADCs with a consistent structure. Each column ADC uses the same multi-stage conversion process, making the system modular and easier to manage despite having multiple ADCs. This universal approach reduces overall system complexity compared to designing unique high-precision conversion circuits for each column.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of determination times and increases the speed of AD conversion, enabling higher-precision and higher-speed operation while improving linearity in subrange connections, thus overcoming the limitations of existing methods.
Implementation Method 1
a plurality of pixels each including a photoelectric conversion element for converting a light signal to an electric signal
Implementation Method 2
Each of the plurality of converters has a retention node for retaining a signal of a pixel which is output via a corresponding vertical read line
Data Source
AI summary
A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N−1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range exceeding the range.