Multi-Stage Controller With Segmented On-Chip Interconnects
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Solution Overview
Problem
Current data storage devices using non-volatile memory face performance bottlenecks due to inefficient communication between the front-end and back-end stages of the controller, leading to delayed data transmission and processing in flash memory operations.
Innovation Solution
A multi-stage controller architecture with an Advanced eXtensible Interface (AXI) bus interconnect system, featuring upper and lower on-chip interconnects, a code loader, front-end and back-end central processing units, and a mailbox system that allows direct communication between stages without relying on the upper interconnect, enabling efficient data transfer and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the code loader uses the upper on-chip interconnect to communicate with the back-end, then the communication path is established, but the communication efficiency is reduced due to channel occupation and delays
Solution Approach 1:
The interconnect system is segmented into upper and lower on-chip interconnects, creating separate communication channels. The code loader communicates through the lower on-chip interconnect, while the host bridge controller uses the upper on-chip interconnect, thereby avoiding channel conflicts and occupation delays.
Solution Approach 2:
The lower on-chip interconnect serves as an intermediary communication channel specifically for the code loader and back-end components. This dedicated intermediate path allows the code loader to communicate efficiently without competing for resources with the host bridge controller on the upper interconnect.
2Productivity
If the code loader connects to the lower on-chip interconnect, then direct communication is enabled, but the system complexity increases due to multiple interconnect paths
Solution Approach 1:
The lower on-chip interconnect serves multiple functions: it connects the code loader to the back-end components for efficient communication, and also provides a dedicated path that doesn't interfere with host bridge operations. This multi-functional design improves productivity without proportionally increasing complexity.
Solution Approach 2:
The system adds a dimensional layer to the communication architecture by introducing the lower on-chip interconnect as a separate communication plane. This allows the code loader to operate in parallel with the host bridge controller, improving overall system productivity through spatial separation of communication paths.
Data Source
AI summary
A technology for controlling non-volatile memory with a multi-stage controller is shown. The multi-stage controller uses an upper on-chip interconnect and a lower on-chip interconnect and includes a serial peripheral bus (SPI) loader, a frond-end central processing unit (FE CPU), and an arbitrator. When being connected to the lower on-chip interconnect, the SPI loader performs code loading for the multi-stage controller. After the SPI loader finishes the code loading, the SPI loader is disconnected from the lower-stage on-chip bus, and the arbitrator connects the FE CPU to the lower on-chip interconnect. This way, the communication channel between the upper on-chip interconnect and the lower on-chip interconnect is not occupied by the FE CPU.