Multi-Stage Divider Unit Scheduling for Concurrent Division
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Solution Overview
Problem
Computing systems face high latency and increased area and power consumption when implementing infrequently used arithmetic operations like division and square root, which can adversely affect system performance.
Innovation Solution
A multiplier unit with multiple stages is configured to perform arithmetic operations, including division and square root, using control circuitry to schedule tasks across stages, allowing concurrent execution of operations and optimizing stage usage to reduce latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated hardware is added to implement division and square root operations, then the functionality and precision of arithmetic operations are improved, but the area usage and power consumption increase
Solution Approach 1:
The patent makes the multiplier unit perform multiple functions by configuring it to execute both multiplication and division/square root operations. The same hardware stages are reused for different arithmetic operations through control circuitry that schedules tasks appropriately, eliminating the need for separate dedicated hardware for each operation type.
Solution Approach 2:
The patent introduces dynamic scheduling of operations across multiple stages. The control circuitry dynamically assigns tasks to available stages based on current utilization, allowing flexible adaptation of hardware resources to meet different computational needs without requiring static dedicated hardware for each operation.
2Adaptability or versatility
If additional circuitry is added to implement division and square root operations, then the functionality of arithmetic operations is improved, but the power consumption increases
Solution Approach 1:
The existing multiplier circuitry is made universal to handle multiple arithmetic operations including division and square root. By reusing the same hardware blocks for different operations through intelligent scheduling, the patent avoids the power overhead of maintaining separate dedicated circuits for each operation type.
Solution Approach 2:
The multiplier unit serves itself by performing multiple arithmetic operations using its existing stages. The control circuitry intelligently schedules tasks to utilize available stages, allowing the hardware to efficiently handle diverse computational requirements without requiring additional power-hungry dedicated circuits.
3Area of stationary object
If a single multiplier unit is used for all arithmetic operations, then the area usage is reduced, but the latency of operations increases due to queuing
Solution Approach 1:
The multiplier unit is segmented into multiple independent stages that can operate in parallel. Each stage can be independently scheduled to work on different parts of the same operation or on different operations simultaneously, reducing the overall latency by eliminating sequential bottlenecks while maintaining compact area usage.
Solution Approach 2:
The patent ensures continuous utilization of all multiplier stages by implementing intelligent task scheduling. Instead of leaving stages idle while waiting for previous operations to complete, the control circuitry continuously assigns new tasks to available stages, maintaining uninterrupted useful action across all hardware resources and reducing operational latency.
4Productivity
If multiple stages are used in the multiplier unit, then the productivity of arithmetic operations is improved, but the device complexity increases
Solution Approach 1:
The multiplier unit is divided into multiple stages that can be independently controlled and scheduled. This segmentation enables parallel processing of arithmetic operations, improving throughput while the modular structure actually simplifies the control logic by allowing independent management of each stage's task assignment.
Solution Approach 2:
The patent implements dynamic scheduling across multiple stages, where the control circuitry adaptively assigns tasks based on real-time stage availability. This dynamic approach improves productivity by maximizing parallel utilization while managing complexity through software-based scheduling rather than complex hardwired control logic.
Data Source
AI summary
A multiplier unit that may be configured to concurrently perform multiple division and square operations is disclosed. The multiplier unit may include multiple stages. Each stage may be configured to perform a corresponding arithmetic operation. Control circuitry coupled to the multiplier unit may be configured to schedule in a given cycle of the plurality of cycles, a respective tasks of a plurality of tasks included in a first operation for execution on a respective stage of the multiple stages. The control circuitry may be further configured to schedule execution of each tasks of a second plurality of tasks included in a second operation during a respective cycle on an unused stage of the multiple stages.